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From: phil@eos.arc.nasa.gov (Phil Stone)
Newsgroups: comp.sys.ibm.pc.misc
Subject: High resolution timing
Summary: How to?
Message-ID: <7675@eos.arc.nasa.gov>
Date: 11 Dec 90 20:52:43 GMT
Reply-To: phil@eos.arc.nasa.gov (Phil Stone)
Organization: NASA Ames Research Center, Calif.
Lines: 21

Excuse me if this is a commonly-discussed topic, but I need a processor-
speed-independent timing utility that gives me millisecond-accurate delay
capability.  Someone is sending me some routines which use Timer 0 on
the 8253 chip; from what I gather, the method is to put the chip into
Mode 2, so that it counts down by ones, allowing its register to be
read directly for the residual count.  The documentation claims that this
has no adverse affects on system Time-of-Day, nor does there seem to be
a "cleanup" routine which sets the timer chip back to its original state
on exit.

Is this indeed a safe method?  If so, why is Mode 3 (counting down by two's
for two loops) even used as the default?

BTW, this utility also accounts for midnight rollover of the counter, so
don't bother warning me about that.  

Thanks for your patience if this is a trivial question, and thanks in
advance for any advice.  Please email if possible; if warranted, I will
post a summary.

		Phil Stone (phil@eos.arc.nasa.gov OR ...!ames!eos!phil)