Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!ut-emx!emx.utexas.edu!star2.cm.utexas.edu!david From: david@star2.cm.utexas.edu (David Sigeti) Newsgroups: comp.sys.ibm.pc.misc Subject: Re: Gateway 2000 Drops Prices Again! Message-ID: Date: 12 Dec 90 23:35:36 GMT References: Sender: news@ut-emx.uucp Organization: University of Texas at Austin Lines: 52 In-reply-to: clong@remus.rutgers.edu's message of 12 Dec 90 12:32:31 GMT In article clong@remus.rutgers.edu (Captain Trott) writes: [Describing the latest prices on a 486 system from Gateway 2000] 25 MHz 486 8 Meg RAM 64K RAM cache Weitek socket 3.5 & 5.25 floppies Windows 3.0 & MS mouse 1024 SVGA board & monitor Fujitsu keyboard 200 MB hard drive MS-DOS 3.3 or 4.01 Toll free technical support. 1 year on site service. $3995! <- NOT a typo. Frankly, this price is so low -- and so far below prices for similar systems from other vendors of equivalent reputation -- that I can't help wondering if there isn't something wrong with the system. I have tried calling Gateway several times and have been unable to get through so I am posting some questions about the system to the net. Does anyone know anything more about the motherboard in this system (manufacturer, BIOS, etc.)? In particular, does it support the 486 burst mode (see below)? Also, does anyone know about the caching algorithm and how well, or poorly, it works with the internal cache and possible burst mode operation? The questions of burst mode support and interaction between internal and external caches seem to me to be worth some discussion. I would be very interested in any information that anyone has on these issues w.r.t. *any* motherboard or system out there. [For those who wonder what I am talking about, the burst mode is a fast way of filling a (128-bit) line in the 486's internal cache. Normally, a memory read requires two clock cycles. When the 486 is filling a cache line, however, it can accept successive (32-bit) reads in a single clock cycle each, if the surrounding circuitry supports it. Thus, filling a cache line can be accomplished in five clock cycles (one to assert the starting address plus one for each 32-bit read) rather than eight clock cycles (two for each 32-bit read).] P. S. I accidently posted an abbreviated version of this note about a half hour before posting this one. I have cancelled it but want to offer my apologies if it is cluttering up anyone's version of this newsgroup. -- David Sigeti david@star2.cm.utexas.edu cmhl265@hermes.chpc.utexas.edu