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From: stevec@bubbyb.Solbourne.COM (Steve Cox)
Newsgroups: comp.sys.m88k
Subject: Re: m88200 cache flushes on DG Aviion
Keywords: m88200 Aviion
Message-ID: <1990Dec10.183632.12559@Solbourne.COM>
Date: 10 Dec 90 18:36:32 GMT
References: <2308@io.UUCP>
Sender: news@Solbourne.COM
Organization: Solbourne Computer, Inc.
Lines: 25

In article <2308@io.UUCP> dbjag@io.UUCP (David Benjamin) writes:
>The reason is kind of hairy, but if you must know, it involves self-modifying
>code which seems to fail on the Aviion when the caches get out of sync.
>There, glad you asked?
>
>This brings up another question.  The code is apparently failing because
>the contents of the two caches different values for the same address.
>Why wasn't this state prevented by the "M-bus snooping" of the 88200's?
>Perhaps my understanding of their function is warped.

yes, i believe your understanding is correct (that the caches are supposed 
to be coherent).  but, perhaps the code you are trying to modify AND THEN 
EXECUTE is not marked as global by the DG operating system.(?)  i believe
that coherency is not maintained for data that isn't marked as global.
it doesn't seem reasonable that this is a problem (or "state" as you say)
in the cache coherency protocol (i.e.  there'd be all sorts of problems
in any multi-88200 system if such a bug existed).

- stevec  

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