Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!uunet!zephyr.ens.tek.com!orca.wv.tek.com!frip!andrew From: andrew@frip.WV.TEK.COM (Andrew Klossner) Newsgroups: comp.sys.m88k Subject: Re: m88200 cache flushes on DG Aviion Message-ID: <9689@orca.wv.tek.com> Date: 10 Dec 90 19:05:16 GMT References: <2308@io.UUCP> <1199@dg.dg.com> Sender: news@orca.wv.tek.com Reply-To: andrew@frip.wv.tek.com Organization: Tektronix, Wilsonville, Oregon Lines: 15 [] "Another solution is to chase the data out of the cache. You can make some memory references that will conflict with the instructions you want to flush and thus chase them out of the cache." But the problem is stale data in the instruction cache. Memory references won't help here; you have to do instruction fetches to flush that data. That would be a worst case of 16 fetches of different instructions, each located at the indicated offset within a page. I suppose it could be done, but it sounds pretty fragile. -=- Andrew Klossner (uunet!tektronix!frip.WV.TEK!andrew) [UUCP] (andrew%frip.wv.tek.com@relay.cs.net) [ARPA]