Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!helps!bigtex!james
From: james@bigtex.cactus.org (James Van Artsdalen)
Newsgroups: comp.sys.novell
Subject: Re: 486 bugs with network card interrupts
Message-ID: <51304@bigtex.cactus.org>
Date: 17 Dec 90 01:25:37 GMT
References: <3733@rwthinf.UUCP>
Reply-To: james@bigtex.cactus.org (James Van Artsdalen)
Organization: Institute of Applied Cosmology, Austin TX
Lines: 31

In <3733@rwthinf.UUCP>, berg%cip-s01.informatik.rwth-aachen.de@unido.bitnet
	wrote:

> According to some computer magazine, there is supposed to be a bug
> in "version 3" of the 486 regarding interrupt processing.

B step I think.  C step does not have the bug (I think, he says,
trying to remember).  But in any case there is a work-around, so even
machines with B step parts should be OK if properly designed.

> The bug (discovered by a UK firm) alledgedly is especially important
> for 'networked' 486's.  They say it is not easy to reproduce the bug.

It was discovered by Compaq in Houston.

The 486 has a four word deep "write buffer".  When the CPU issues a
write, it is put in the queue and written as soon as the bus is idle.

When the 486 receives an interrupt request, it does two special
"interrupt acknowledge" cycles.  The first one is a "dummy" cycle that
causes the interrupt controller to latch its interrupt input pins, and
the second acknowledge cycle reads the actual vector from the
interrupt controller.

Those two interrupt acknowledge cycles are supposed to be guaranteed
adjacent.  The bug is that sometimes the write buffer can do a cycle
between the two INT/ACK cycles.  Some interrupt controllers can't
handle this.
-- 
James R. Van Artsdalen          james@bigtex.cactus.org   "Live Free or Die"
Dell Computer Co    9505 Arboretum Blvd Austin TX 78759         512-338-8789