Path: utzoo!censor!geac!torsqnt!news-server.csri.toronto.edu!cs.utexas.edu!usc!zaphod.mps.ohio-state.edu!mips!winchester!mash From: mash@mips.COM (John Mashey) Newsgroups: comp.arch Subject: Re: Why do RISCs use (*not* need) fewer transistors? Message-ID: <44130@mips.mips.COM> Date: 17 Dec 90 02:32:21 GMT References: <1990Dec14.001129.988@Neon.Stanford.EDU> <18164@neptune.inf.ethz.ch> Sender: news@mips.COM Reply-To: mash@mips.COM (John Mashey) Organization: MIPS Computer Systems, Inc. Lines: 111 In article <18164@neptune.inf.ethz.ch> brandis@inf.ethz.ch (Marc Brandis) writes: >In article <1990Dec14.001129.988@Neon.Stanford.EDU> hoelzle@Neon.Stanford.EDU (Urs Hoelzle) writes: >>The integer part of a typical RISC can be implemented with about 100K >>transistors. Current impementation technology allows >1M >>transistors/chip (e.g. i486, 68040). Why don't current RISC >>implementations take advantage of the extra transistors and put a >>large cache on the chip? And/or an FPU? For example (as far as I >>know), typical SPARC chips neither have an on-chip FPU nor a large >>cache; same for MIPS. >This is only true for what you find in current machines, but it is not true >for chips. E.g. the new MIPS R3300 (or maybe R3400, I do not exactly remember >the number) contains the FPU and caches on chip. There are SPARC >implementations that have cache on chip. There are RISC CPUs like the i860 >or the IBM RS/6000 that have around 1 million transistors on a chip (actually, >the RS/6000 uses 9 chips with almost 8 million transistors as a whole). >>One reason for a lower transistor count might be cost - but having >>separate FPU or MMU chips doesn't exactly reduce system cost. Or does >>the better yield of the small chips outweigh the extra cost of having >>several chips instead of just one? > >One or two years ago it may have been that the better yield would result in >lower cost as a whole. But the picture is changing. I think in one or two >years you will find a lot RISC workstations containing CPUs with 1 million >transistors. It might be good to try stepping back up a level to the generic rules, then look at the specifics again. GENERIC: 1) For a system (such as a UNIX system), you need: 1) Overall control 2) Integer datapath 3) FPU 4) MMU 5) Caches (at least 1 level) 6) Cache control 7) Glue&gunk&support to outside world 2) At any given time, within "reasonable" cost and "reasonable" testability, and "reasonable" time-to-market, there are limits on: a) The maximum size of chip you can build b) The speed of the internal circuitry c) The speed of external interface Note that c) can often be a worse contraint than b). Note also, that shrinking a chip increases yield, and over time, lowers cost, although at some point, the limit becomes the pad-ring, i.e., the pads have a minimal possible size, even though you could shrink the insides of the chip more. 3) There are plenty of different ways to partition this: MIPS SPARC 88K IBM RS6000 (in SS2) 1. cntl R3000 601 IU 88100 ICU 2. int R3000 601 IU 88100 FXU 3. fpu R3010 TI FPU 88100 FPU 4. MMU R3000 SRAMs 88200s ICU+FXU 5. cach SRAMs SRAMs 88200s ICU + 2-4 DCUs 6. cc R3000 extlogic 88200 ICU+FXU+DCU 7. glue WBs extlogic - SCU 4) In the round in which most MIPS/SPARC/88K chips on the market were designed, you couldn't get everything on one chip, of course, The Intel 486 & 860, and Motorola 68040 essentially integrate all of these things. 5) Amongst the MIPS camp, there are chips with R3000+R3010 stuck together (Performance Semiconductor), which can help performance & cost; and embedded control chips (IDT, LSIL) which integrate up to 8KB I-cache & 2KB D-cache with an R3000 + buffering (i.e., 1,2,5,6,7, and sometimes 4, but not 3) together. Intel 960s come in various combinations, some of which are similar to these. 6) In SPARCland, the Solbourne million-transistor chip integrates everything (BTW, can somebody confirm/deny: 12 Specmarks at 25MHz, or at 33MHz?) Embedded control versions are also supposed to be coming. 7) As to why there aren't more million-transistor RISCs around, when there were already 486s, there is a simple answer: Some people started earlier, some started later: a) Intel certainly knows how to build micros, and started on the design (according to my sources, somebody at Intel correct me if I'm wrong) in 1H86, getting chips out in 1989. In 1H86, there were no SPARC chips, and only the earliest MIPS R2000s, with early systems going out in 3Q86. b) Next-generation RISC chips from MIPS (R4000) and Sun (Viking) should come out in 1991, and are reputed to be pretty aggressive chips with a lot of stuff crammed in there. I don't know when they started; we started (effectively) about 30-33 months after Intel. 8) The big technology jump is when you get everything on 1 CPU, i.e., at least 1-6 (sometimes 7 is separate). 9) Finally, note that with a million transistors, you don't get to have a "big" on-chip cache, i.e., you get 8-16KB, and it's a horrible impediment to the faster machines. You'd really like to have 64KB, but that has to wait a round or so, depending on how much space the rest of your design takes. -- -john mashey DISCLAIMER: UUCP: mash@mips.com OR {ames,decwrl,prls,pyramid}!mips!mash DDD: 408-524-7015, 524-8253 or (main number) 408-720-1700 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086