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From: my@dtg.nsc.com (Michael Yip)
Newsgroups: comp.arch
Subject: I cache/D cache (was: Re: Why do RISCs use fewer transistors?
Summary: What is a good I cache to D cache ratio?
Keywords: Cache, MIPS, IDT, RISC
Message-ID: <1589@berlioz.nsc.com>
Date: 17 Dec 90 04:50:46 GMT
References: <1990Dec14.001129.988@Neon.Stanford.EDU> <18164@neptune.inf.ethz.ch> <44130@mips.mips.COM>
Reply-To: my@berlioz.UUCP (Michael Yip)
Organization: National Semiconductor, Santa Clara
Lines: 26

In article <44130@mips.mips.COM> mash@mips.COM (John Mashey) writes:
>5) Amongst the MIPS camp, there are chips with R3000+R3010 stuck
>together (Performance Semiconductor), which can help performance & cost;
>and embedded control chips
>(IDT, LSIL) which integrate up to 8KB I-cache & 2KB D-cache with
>an R3000 + buffering (i.e., 1,2,5,6,7, and sometimes 4, but not 3)
>together.   Intel 960s come in various combinations, some of
>which are similar to these.

Can someone tell me why IDT or LSI chose to integrate 8K I-cache and
2K D-cache?  From what I understand, a 2K I-cache and 8K D-cache may
yield a better overall cache hit.  I always think that a smaller
I-cache is "enough" to do the job (so that small loops and sequencial
instructions get executed from the cache and since data references is
not as localize as instruction references, therefore a big D-cache
will help hit rate more.  Can someone tell me if I am totally wrong?
(Sorry, I work on FDDI and don't know much about processor
architecture.)

By the way, can someone tell me the I-cache size that is needed to
achieve X percent (say 90%) of I-cache hit for a particular CPU camp?
[This should not be depended on secondary cache or main memory 
latency, right?]

-- Mike Yip
   my@dtg.nsc.com