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From: mash@mips.COM (John Mashey)
Newsgroups: comp.arch
Subject: Re: I cache/D cache (was: Re: Why do RISCs use fewer transistors?
Keywords: Cache, MIPS, IDT, RISC
Message-ID: <44136@mips.mips.COM>
Date: 17 Dec 90 17:36:49 GMT
References: <1990Dec14.001129.988@Neon.Stanford.EDU> <18164@neptune.inf.ethz.ch> <44130@mips.mips.COM> <1589@berlioz.nsc.com>
Sender: news@mips.COM
Reply-To: mash@mips.COM (John Mashey)
Organization: MIPS Computer Systems, Inc.
Lines: 46

In article <1589@berlioz.nsc.com> my@berlioz.UUCP (Michael Yip) writes:
>In article <44130@mips.mips.COM> mash@mips.COM (John Mashey) writes:
>>5) Amongst the MIPS camp, there are chips with R3000+R3010 stuck
>>together (Performance Semiconductor), which can help performance & cost;
>>and embedded control chips
>>(IDT, LSIL) which integrate up to 8KB I-cache & 2KB D-cache with
>>an R3000 + buffering (i.e., 1,2,5,6,7, and sometimes 4, but not 3)
>>together.   Intel 960s come in various combinations, some of
>>which are similar to these.

>Can someone tell me why IDT or LSI chose to integrate 8K I-cache and
>2K D-cache?  From what I understand, a 2K I-cache and 8K D-cache may
>yield a better overall cache hit.  I always think that a smaller
>I-cache is "enough" to do the job (so that small loops and sequencial
>instructions get executed from the cache and since data references is
>not as localize as instruction references, therefore a big D-cache
>will help hit rate more.  Can someone tell me if I am totally wrong?
>(Sorry, I work on FDDI and don't know much about processor
>architecture.)

As noted below, there's no one right answer.  However, observe that
the high-end Adobe RIP boards use R3000s, and that a really obvious use
for the IDT or LSIL parts is for cheap-but-fast laser printers,
and that executing Postscript or equivalent is a LOT of code,
and that 8K I-cache might help, whereas no reasonable cache would ever
hold all of an image anyway. 

>By the way, can someone tell me the I-cache size that is needed to
>achieve X percent (say 90%) of I-cache hit for a particular CPU camp?
>[This should not be depended on secondary cache or main memory 
>latency, right?]
This is impossible to answer in general: it depends heavily on the
type of application:
	a) Commercial environments like big I & D caches, because they
	execute OS & DBMS code and multi-task as lot, and often want
	good hit rates for DBMS buffers.
	b) Pure scientific machines get away with smaller I-caches,
	and would like either huge D-caches, or really high memory
	bandwidth, or both, since they spend their time in small loops
	crunching thru arrays.
	c) Embedded control varies all over the map.
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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