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From: brett@cayman.amd.com (Brett Stewart)
Newsgroups: comp.arch
Subject: Re: I cache/D cache (was: Re: Why do RISCs use fewer transistors?
Keywords: Cache, MIPS, IDT, RISC
Message-ID: <1990Dec17.162219.11424@mozart.amd.com>
Date: 17 Dec 90 16:22:19 GMT
References: <18164@neptune.inf.ethz.ch> <44130@mips.mips.COM> <1589@berlioz.nsc.com>
Sender: usenet@mozart.amd.com (Usenet News)
Organization: Advanced Micro Devices, Inc., Austin, Texas
Lines: 21

In article <1589@berlioz.nsc.com> my@berlioz.UUCP (Michael Yip) writes:
>
>By the way, can someone tell me the I-cache size that is needed to
>achieve X percent (say 90%) of I-cache hit for a particular CPU camp?
>[This should not be depended on secondary cache or main memory 
>latency, right?]

You might want to look at "Aspects of Cache Memory and Instruction Buffer
Performance"  by Mark Donald Hill, Report No. UCB/CSD 87/381 from
Berkeley CSD. (Mr. Hill's thesis)

There is a very nice quantitative analysis there.  One nice thing
about it is it talks about the implication of Branch Target Cache buffers,
(of which our Am29000 is the only one in a single-chip commercial
RISC)  and its impact on performance, and it contains quantitative information
to refute many of the conclusions that have been authoritatively advanced
in this news string.
Brett Stewart
Advanced Micro Devices, Inc.           +1 512 462 5051 FAX
5900 E. Ben White Blvd MS561           +1 512 462 4336 Telephone
Austin, Texas 78741      USA           brett@cayman.amd.com