Path: utzoo!attcan!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!sdd.hp.com!mips!prls!pyramid!ctnews!88opensi!dave
From: dave@88opensi.88open.ORG (Dave Cline)
Newsgroups: comp.arch
Subject: Re: m88200 cache flushes on DG Aviion
Summary: cache flush interface, SVR4
Message-ID: <1990Dec17.183131.20374@88opensi.88open.ORG>
Date: 17 Dec 90 18:31:31 GMT
References: <1199@dg.dg.com> <4322@photon.oakhill.UUCP> <44118@mips.mips.COM>
Organization: 88open Consortium Ltd., San Jose
Lines: 19

In article <44118@mips.mips.COM>, mash@mips.COM (John Mashey) writes:
> 
> WHAT'S THE PROGRAMMATIC INTERFACE FOR CACHE-FLUSHING (and any other
> cache-manipulation operations) on your favorite machine?
> ARE THERE ANY STANDARDS FOR SCUH THINGS ACROSS VENDORS? (I can hope :-)
> 
> If nobody is working on standardizing the programmatic interface,
> we probably should be, as a service to the industry...

SVR4 defines interfaces for cache flushing.

In SVID3, see msync(KE_OS) or the foundation interface, memcntl(RT_OS)

These are required by the generic ABI.

Dave Cline                            uucp: ...uunet!88opensi!dave
88open Consortium, Ltd.                     dave@88open.org
100 Homeland Court, Suite 800
San Jose, CA 95110