Path: utzoo!mnetor!tmsoft!torsqnt!news-server.csri.toronto.edu!cs.utexas.edu!usc!julius.cs.uiuc.edu!rpi!crdgw1!crdos1!davidsen
From: davidsen@crdos1.crd.ge.COM (Wm E Davidsen Jr)
Newsgroups: comp.arch
Subject: Re: Let's pretend
Keywords: Intel, 586, windows
Message-ID: <3059@crdos1.crd.ge.COM>
Date: 18 Dec 90 19:52:09 GMT
References: <3042@crdos1.crd.ge.COM> <1990Dec18.082623.16648@kithrup.COM> <1990Dec18.141944.5041@athena.cs.uga.edu> <1990Dec18.115605.7411@jarvis.csri.toronto.edu>
Reply-To: davidsen@crdos1.crd.ge.com (bill davidsen)
Organization: GE Corp R&D Center, Schenectady NY
Lines: 26

In article <1990Dec18.115605.7411@jarvis.csri.toronto.edu> jonah@dgp.toronto.edu (Jeff Lee) writes:

| What *can* be annoying is having to save all registers in every
| exception handler.  Having a separate set of GP registers for each
| processor mode could turn "traps" and "interrupts" into almost
| instantaneous co-routine switches.  The tricky part might be flushing
| the pipeline correctly -- I don't know how easily this can be done.
| My caveat on this is that these additional registers should look just
| like the normal GP registers so that kernel code can be compiled with
| the same compiler as user code.  Only the context save/restore code
| should need to access registers in another register bank.  The PDP10
| used to have different user/system register banks so it can be done.

  You've just described the Z80. 

  I would think it useful to (a) disable interrupts while the registers
were swapped, and (b) allow access to the alternate set. This and an
instruction to "save alternate regs and enable ints" could be used if
more than a few instructions were needed to service the condition. And
the converse, of course.

  The Z80 was fast for its day when that technique was used. I had
"parallel port NFS" under CP/M to get access to drives on other machines.
-- 
bill davidsen	(davidsen@crdos1.crd.GE.COM -or- uunet!crdgw1!crdos1!davidsen)
    VMS is a text-only adventure game. If you win you can use unix.