Path: utzoo!censor!geac!torsqnt!news-server.csri.toronto.edu!cs.utexas.edu!usc!csun!kithrup!sef
From: sef@kithrup.COM (Sean Eric Fagan)
Newsgroups: comp.arch
Subject: Re: Let's pretend
Keywords: Intel, 586, windows
Message-ID: <1990Dec19.051337.3670@kithrup.COM>
Date: 19 Dec 90 05:13:37 GMT
References: <1990Dec18.141944.5041@athena.cs.uga.edu> <1990Dec18.173039.882@kithrup.COM> <1990Dec18.202842.11771@athena.cs.uga.edu>
Organization: Kithrup Enterprises, Ltd.
Lines: 29

In article <1990Dec18.202842.11771@athena.cs.uga.edu> is@athena.cs.uga.edu ( Bob Stearns) writes:
>Note that when I read "more registers" I think
>in terms of machines like the CYBER 205 with its 256 64bit registers or even
>larger sets. 

Ah.  A misunderstanding... 8-)

I just mentioned the 205 to someone in a response to my posting (remember
that the ETA-10 is a faster and better 205).

However, recall that we were discussing the *86, a machine which has *6*
registers available for "general purpose" use, which really aren't (lots and
lots of instructions require certain registers, or at least work better with
them).

More on the subject of context switching:  the Elxsi had something like 16
sets of registers on board.  During a context switch (e.g., from one thread
to another [no supervisor mode on the machine]), it just used the next
available set of registers.  The hardware *knew* about threads and whatnot,
so this was feasible.  But I can imagine someone like MIPS or Sun (for the
Sparc, of course) putting a few different sets on board, whose sole purpose
would be to act as a buffer when handling faults and whatnot.  Sort of like
register windows, only for context switches, not subroutine calls.

-- 
Sean Eric Fagan  | "I made the universe, but please don't blame me for it;
sef@kithrup.COM  |  I had a bellyache at the time."
-----------------+           -- The Turtle (Stephen King, _It_)
Any opinions expressed are my own, and generally unpopular with others.