Path: utzoo!censor!geac!torsqnt!news-server.csri.toronto.edu!cs.utexas.edu!wuarchive!uunet!crdgw1!crdos1!davidsen
From: davidsen@crdos1.crd.ge.COM (Wm E Davidsen Jr)
Newsgroups: comp.arch
Subject: Re: Let's pretend
Keywords: Intel, 586, windows
Message-ID: <3069@crdos1.crd.ge.COM>
Date: 19 Dec 90 15:13:15 GMT
References: <3042@crdos1.crd.ge.COM> <1990Dec18.082623.16648@kithrup.COM> <3058@crdos1.crd.ge.COM> <1990Dec19.060521.16051@iecc.cambridge.ma.us>
Reply-To: davidsen@crdos1.crd.ge.com (bill davidsen)
Organization: GE Corp R&D Center, Schenectady NY
Lines: 48

In article <1990Dec19.060521.16051@iecc.cambridge.ma.us> johnl@iecc.cambridge.ma.us (John R. Levine) writes:

	[ lots of good stuff ]

	[ stuff about ints being painfully slow ]

|                                Also, device interrupts on the 486 use the
| same creaky method that the 8088 did.  There's a single interrupt line, and
| when the interrupt happens it accepts a vector from the interrupt controller.

  Yes, isn't that a nice general solution? It allows simple devices to
create interrupts without needing an interrupt controller in the system
at all, and yet give 256 discrete interrupts in the vector.

| That controller is still an 8259A which only has 8 interrupt lines unless you
| cascade them which is a kludge.  There is no easy way to mask some device
| interrupts without masking them all (you can stuff commands to the 8259 but
| it's slow and clumsy.)  

  Here I disagree. While the cascade does cause some latency, it allows
groups of interrupts to be enabed and disabled at once, and for some to
be edge and some level triggered. How slow and clumsy can a two
instruction sequence load to register and out register to port be?

|                         An interrupt level register that the kernel could
| manage easily, sort of like the PDP-11 scheme, would be helpful.

  The 8259 has a mode which disables all low priority interrupts while
the current interrupt is being serviced. And one which takes them at
single priority "round robin."

|                                                                   To support
| this without having a dedicated interrupt line for each device needs a bus
| protocol so that devices can post a request for interrupt including the
| interrupt number, and the CPU can come back later and say "number 17, your
| interrupt is now taken."  If we have all level-triggered interrupts, we could
| even get by without the call back.

  This is a bus issue, I think.

  Actually this whole thing is taking place off chip, so you can do
anything you want for interrupts. You can use a multiplexed scheme to
reduce the number of lines, with or without the 8259. It's not part of
the CPU, except in the 80186 which had a clock, interrupt controller,
and a couple of serial i/o ports (1 bit) built in.
-- 
bill davidsen	(davidsen@crdos1.crd.GE.COM -or- uunet!crdgw1!crdos1!davidsen)
    VMS is a text-only adventure game. If you win you can use unix.