Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!swrinde!zaphod.mps.ohio-state.edu!mips!winchester!mash From: mash@mips.COM (John Mashey) Newsgroups: comp.arch Subject: Re: Let's pretend Keywords: Intel, 586, windows Message-ID: <44256@mips.mips.COM> Date: 20 Dec 90 22:55:21 GMT References: <3058@crdos1.crd.ge.COM> <1990Dec19.052338.3911@kithrup.COM> <1990Dec19.143749.3216@ux1.cso.uiuc.edu> <1990Dec19.222932.1446@kithrup.COM> <3080@crdos1.crd.ge.COM> Sender: news@mips.COM Reply-To: mash@mips.COM (John Mashey) Organization: MIPS Computer Systems, Inc. Lines: 50 In article <3080@crdos1.crd.ge.COM> davidsen@crdos1.crd.ge.com (bill davidsen) writes: >In article <1990Dec19.222932.1446@kithrup.COM> sef@kithrup.COM (Sean Eric Fagan) writes: > >| The instruction set was designed to be efficient in a different era. Now, >| it's not so efficient. Why do you think that RISC chips, or even 68k's, are >| getting such higher performance? > > Take a look at SPECmarks and rething that last one. The 25 MHz 486 >falls between the SS1 and SS+, 33MHz is off the shelf, 40MHz is >scheduled in a few months and engineering samples were out for board >design, average cycles per instruction is something like 1.3, fairly >close to the actual performance of most RISC machine. > My point is that the term "such higher performance" is misleading, the >486 is comparable in performance to the typical single user workstation >RISC CPU (not many people get a 4/490 for personal use). 1) Generally, the only people who REALLY know the CPI are the architects of a given CPU, because there's no simple way to measure. However, 1.3, I think is rather far off, as shown below. 2) A reasonable approximation, that can actually be measured, is MHz/VAx-mips. (It actually happens that this is pretty close approximation for MIPS machines and others with grossly-similar instruction sets, I think). 3) If you look at MHz/SPEC-integer (a measureable idea of VAX-mips), you find things like (numbers thru Fall SPEC): MHZ SPECint M/S Cache size machine 25 12.4 2.0 64K Sun SS1+, IPC 25 13.3 1.9 128K Intel 486 (from Intel perf brief) 33 19.7 1.7 128K Sun SS/49* (NOT a desktop) 25 19.4 1.3 64K MIPS Magnum 3000 (1.288) 20 15.8 1.3 40K IBM RS6000/520 (1.265) I.e., to be more precise: a 486, with desktop/deskside package, is comparable in integer performance (although not in FP) to a desktop SPARC with a smaller cache. Also, recall yesterday's postings about taking are with compiler choice, timing etc, so all of this has caveats. However, it should be clear that the 486 does NOT have the MHZ/Spec of the more efficient RISCs; in addition, although I don't know exactly what a 486+cache+cache control costs, the MIPS case above costs something like $300-$400, and I suspect that's a bit les than the 486 case. -- -john mashey DISCLAIMER: UUCP: mash@mips.com OR {ames,decwrl,prls,pyramid}!mips!mash DDD: 408-524-7015, 524-8253 or (main number) 408-720-1700 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086