Path: utzoo!censor!geac!torsqnt!news-server.csri.toronto.edu!cs.utexas.edu!usc!apple!mips!winchester!mash From: mash@mips.COM (John Mashey) Newsgroups: comp.benchmarks Subject: Re: benchmark evaluations Message-ID: <44228@mips.mips.COM> Date: 19 Dec 90 22:42:41 GMT References: <12220@hubcap.clemson.edu> <44157@mips.mips.COM> <6434@mace.cc.purdue.edu> <44201@mips.mips.COM> Sender: news@mips.COM Reply-To: mash@mips.COM (John Mashey) Organization: MIPS Computer Systems, Inc. Lines: 55 In article tom@ssd.csd.harris.com (Tom Horsley) writes: >Speaking of full disclosures, the latest SPEC reports (which are >unfortunately locked in the office next to me so I can't get to them right >now to pull off the exact numbers) have a lot of different numbers for MIPS >based machines. Just using the 25MHZ machines as an example (I think thats >an R3000?) there are numbers that range from somewhere around 16-17 >SPECmarks to 19-20 SPECmarks for machines that seem nearly identical from >everything described in the SPEC newsletter. They have the same clock rate, >the same cache size, about the same amount of main memory, and are using the >same compilers. The question then becomes: > "What's different?" >I tend to suspect memory bandwidth, but maybe they have different float >units? Can anyone tell me the real reason the numbers vary so much? let me tell you what it isn't: different floating point units. Every R3000 ever built, if it uses FP at all, uses the same R3010 FPU. Here are some of the things that do make a difference: 1) Cache size 2) Cache line size: refill size might be 8, 16, or maybe even 4 words. 3) Write buffering (different machines have different depths of write-buffers, 4, or 8; some may do byte-gathering of byte writes, and flush the relevant cache word; others may do a 2-cycle read-check tag-write partial word if found in cache). 4) Speed of accepting writes to memory. This is usually 1 every other cycle, but depends on interleaving and use/nonuse of page-mode DRAMs, where you get fast access if the reference is in the same page as previous one, but slower to switch pages. 5) Main memory system: some may have a single path to memory, and get stalled if I/O is going on; others may have a private-memory-bus and a separate VME bus interface with big FIFOs so they interfere less. 6) Presence of secondary cache: some systems (multiprocessors) have these, and they can affect the benchmarks. 6) How the system got there, i.e., maybe it was a MIPS chip stuck into an existing bus structure, or maybe it was an upgrade required to use memory boards from previous version, where latency cycles get added because of some clock-rate matching that has to be done. SO..... From PC benchmarks, one can see that different vendors get different performance from same chip at same clock. It's even more so with people building more complex and/or higher-performance products. (For people who've seen the "car" talk, whereby computers are equated to cars, the memory system is equated to a turbo-charger; like cars, it can make a big difference.) -- -john mashey DISCLAIMER: UUCP: mash@mips.com OR {ames,decwrl,prls,pyramid}!mips!mash DDD: 408-524-7015, 524-8253 or (main number) 408-720-1700 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086