Path: utzoo!mnetor!tmsoft!torsqnt!news-server.csri.toronto.edu!cs.utexas.edu!sdd.hp.com!hplabs!hpda!hpcuhb!hpindda!ananth From: ananth@hpindda.cup.hp.com (AP Anantharaman) Newsgroups: comp.dcom.lans Subject: Re: FDDI chip set (SUPERNET) query .... Message-ID: <3530009@hpindda.cup.hp.com> Date: 18 Dec 90 00:33:54 GMT References: <1990Dec14.222742.8116@cec1.wustl.edu> Organization: HP Information Networks, Cupertino, CA Lines: 31 / hpindda:comp.dcom.lans / kapoor@wuee1.wustl.edu (Sanjay Kapoor) / 2:27 pm Dec 14, 1990 / What is this SUPERNET chipset ? Who manufactures them ? Are there any FDDI cards made with this chipset ? ananth@hpda --------------------------------------------------------------------------- I have a couple a questions related to the SUPERNET chip set. Q) Given that SUPERNET does not impose a restriction on the response time of the interrupt latencies, what are the response times generally preffered? Of course it does depend on the interrupt priorities, worst case traffic patterns of frame arrival etc. Some real numbers is what I am looking for. Also in terms of performance, is it a good idea to run higher layer protocols and do SUPERNET housekeeping within the same chip? Higher layer protocols like say TCP/IP etc? This is because besides DPC, and Node processor, the third DMA channel that RBC services is a chip that processes only the data frames. All control frames are routed to the node processor. Suggestions/advice/Solutions are all greatly welcome. Thanks -Sanjay Kapoor kapoor@wuee1.wustl.edu ----------