Path: utzoo!attcan!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!uunet!indetech!vsi1!hsv3!U.N.Owen
From: U.N.Owen@hsv3.UUCP (U.N.Owen)
Newsgroups: comp.lsi
Subject: Verilog test vectors into LSI .TPT and .SCL files anyone ?
Message-ID: <6294@hsv3.UUCP>
Date: 18 Dec 90 01:28:24 GMT
Organization: \/Svn
Lines: 14


 
Hi folks,

	(I hope this is the right group for this question...)

		Anyone know of a way to convert verilog simulations
	into LSI ASIC test vector files (TPT and SCL)?

	Please email... 
Thanks

-- 
...ames!vsi1!v7fs1!U.N.Owen    **** Aunt Agatha  Where are you ? :-) ********