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From: tilmann@mcshh.hanse.de (Tilmann Reh)
Newsgroups: comp.os.cpm
Subject: Re: Z80DMA & DART
Summary: her's the answer
Message-ID: <8491@mcshh.hanse.de>
Date: 9 Dec 90 11:09:50 GMT
References: <7imuT1w163w@cynic.wimsey.bc.ca>
Lines: 53



Hello.

pevans@cynic.wimsey.bc.ca (Phillip Evans) writes:

> The DMA gets sent 08hex as one of the first instructions - then it's
> not used again by the prom.  The DART gets sent this sequence:
> 18 01 00 03 C1 04 44 05 68 00  (the last 00 might be superfluous)

> Question ONE: What DOES the set of initialisation bytes do?

a) The 08h for the DMA means: Port B is I/O and decrements.
   That seems to be not the whole initialization :-)
b) 18    : channel reset
   01 00 : all interrupts disable
   03 C1 : rx 8 bit, no handshake, rx enable
   04 44 : x16 clock mode, 1 stopbit, no parity
   05 68 : dtr & rts inactive, tx 8 bit, tx enable
   00    : reset internal register pointer

> Question TWO: What I need to know here are the meanings of the 
> bits 0, 4, 5, and 6; 

The DART status register is as follows:
bit 7 : break
bit 6 : not used
bit 5 : cts
bit 4 : ri
bit 3 : dcd
bit 2 : tx buffer empty
bit 1 : int. pending (ch. A only)
bit 0 : rx char available

> what happens when the status register is loaded with the returned byte 
> after it is masked with 0000 0001 binary; and what happnes when it is 
> loaded with 030hex.
 
Be aware that you need only two addresses per channel, so the addresses of
the status register and the command register are equal (see init part).
So sending 00 to that address resets the internal register pointer (so that
the next read-access will safely get the status register).
The second output does exactly the same, as the value in A will always be 00.
Outputting 30h to the command register means 'error reset'.

Hope this may help you.
 
> Thanks in advance to anyone who can answer these questions for me...

no reason.

Tilmann Reh			tilmann@mcshh.uucp
				tilmann@mcshh.hanse.de