Path: utzoo!censor!geac!torsqnt!news-server.csri.toronto.edu!cs.utexas.edu!wuarchive!rex!uflorida!travis!hrshcx!steved
From: steved@hrshcx.csd.harris.com (Steve Daukas)
Newsgroups: comp.realtime
Subject: Real-time Harris (was Re: Real Time Risc)
Message-ID: <891@hrshcx.csd.harris.com>
Date: 19 Dec 90 18:45:17 GMT
Organization: Harris Computer Systems - Fort Lauderdale, Fl.
Lines: 63
Location: Boston Office


Greetings,

My appologies for not responsing to some of your questions
concerning an earlier post of mine... I have been tied-up.

DISCLAIMER:  I do not speak for Harris proper.  I read this group
and respond on my own.  Information given is published and can be 
obtained officially by contacting your local Harris Computer Systems
Division office, or by calling (800) 666-4544 and asking for the
sales and marketing extension (this is in Florida).  I am not a
sales person, just an engineer...  I have no authority from Harris to
speak on Harris' behalf!

I don't remember the specific questions, but they were in
response to some numbers I gave as follows:  5 usec interrupt 
response time and less than 50 usec context switch times.  These
numbers reflect response times for Harris' CX/RT and CX/UX
Unix kernals running on the Night Hawk systems (M68030 and M88100
based).  Keep in mind that CX/UX and CX/RT are only available on
a Harris machine...

Someone asked how this was accomplished.  Well,  I can't give away
any secrets, but I will describe the general concepts:

Essentially,  we've added some capability to the context switcher
that enhances the context switcher's ability to make tasks runnable
for a given run queue (we are talking about multi-processors).  This,
combined with a multi-threaded preemptable kernal, allows many tasks
to be running in the kernal or device driver at one time.  When an
interrupt comes along, the handler can immediately run while other
tasks are still active.  The kernal itself is symmetric, so any task
on any CPU has equal access.  Also, all interrupts are vectorable to any
CPU.  An example for device drivers is that SPL8 doesn't actually do what 
you might think or are used to.

An example real-world test follows:

Using an external edge-triggered interrupt, a VME based DR11 interface, 
and a scope, an experiment was set up to see the delta between the interrupt 
and data available from the DR11.  This delta was much less than 50 usec.  
So, this includes the interrupt response, handler, context switch, and 
processing necessary for the DR11 to start sending data.  The CX/RT kernal 
gives much less than 50 usec (the same number) consistantly, while the CX/UX 
kernal has some gitter (CX/UX is the non-realtime version, hence the 
nondeterministic gitter).

There are many other tests done for specific requirements, as well as the
normal industry standard benchmarks.  Obviously, customer specific info is
not given out.  The other performance data can be obtained by contacting a
local Harris CSD rep.

Sorry I can't respond directly to the questions, I don't have access to 
old posts at my site...

Steve
--

Stephen C. Daukas              | sdaukas@csd.harris.com  
Harris Corporation             | uunet!hcx1!misg!sdaukas  
Computer Systems Division      | (617) 221-1834, (617) 221-1830

     "Old MacDonald had an agricultural real estate tax abatement."