Path: utzoo!utdoe!generic!pnet91!ericmcg
From: ericmcg@pnet91.cts.com (Eric Mcgillicuddy)
Newsgroups: comp.sys.apple2
Subject: Re: Adding an MMU
Message-ID: <308@generic.UUCP>
Date: 20 Dec 90 23:50:06 GMT
Sender: root@generic.UUCP
Organization: People-Net [pnet91], Etobicoke, ON
Lines: 32

The WDC spec sheets do not go into detail on which instructions do not work
properly with /ABORT, however there are some provisos listed.

The processor status will be modified if /ABORT is asserted after cycle 3 of
an RTI.

The Processor status will be modified if /ABORT is asserted after a modify
cycle.

The PBR will be set to 00 if after cycle 2 of any hardware or software
interupt and the DBR is also set to 00 if in emulation mode.

/ABORT should not be held low for more than 1 cycle. After 1 cycle, the ABORT
Latch is reset and will thus ABORT the ABORT interupt. 

As far as I can tell, /ABORT will only cause problems if used as an
asynchronous interupt. Insuring that it is not triggered too far away from the
positive transition of phi2 ( within tpcs nS) should prevent any badness from
occurring, regardless of instruction. Leventhal merely suggests not using the
ABORT vector and goes into no detail on what problems could be created.

I vote that you modify GSOS rather than writing UNIX GS. I would certainly buy
the card if it were compatible. 

BTW, I suggest you contact Tony Faddell, the ASIC '816 apparently 'corrects'
the problems with /ABORT, he would know the most this particular interupt.

Also BTW, what about using the newer 68852? I believe that it is a bit faster
and might have a larger table cache on chip.

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