Path: utzoo!mnetor!tmsoft!torsqnt!news-server.csri.toronto.edu!cs.utexas.edu!sdd.hp.com!ucsd!ucbvax!bloom-beacon!vaxeline!bootsie!olson From: olson@bootsie.UUCP (Eric Olson) Newsgroups: comp.sys.mac.programmer Subject: Re: Increment (Was Re: Pascal deficiency)? Message-ID: <44@bootsie.UUCP> Date: 18 Dec 90 09:48:45 GMT References: <1990Dec17.160242.5095@phri.nyu.edu> <1990Dec17.172613.7941@cs.umn.edu> <1990Dec18.001753.3756@Neon.Stanford.EDU> <49832@cornell.UUCP> Reply-To: olson@bootsie.UUCP (Eric Olson) Organization: Lexington Software Design, Lexington, MA Lines: 83 In article <49832@cornell.UUCP>, many people calmly discuss: >>>Actually, this would have to be > >>->x++: LOAD X >>-> INC X >>-> STORE X > >>>Unless you have an instruction to increment variables in memory! >>...lets just look at the code MPW C generates for just such constructs: > [Next line quoted out of position -EO] >This is good information, but how many cycles does each of these take? ; For 68000, no wait state memory > >> i = i+1; >> MOVE.L i,D2 ; 16(4/0) >> ADDQ.L #$1,D2 ; 8(1/0) >> MOVE.L D2,i ; 16(2/2) > ;=40(7/2) >> i++; >> MOVE.L i,D2 ; 16(4/0) >> ADDQ.L #$1,i ; 12(1/2) + 12(3/0) > ;=40(8/2) >> ++i; >> ADDQ.L #$1,i ; 12(1/2) + 12(3/0) > ;=24(4/2) ; For 68020, no wait state memory > ; Best Case Cache Case Worst Case >> i = i+1; >> MOVE.L i,D2 ; 3(1/0/0) 7(1/0/0) 9(1/2/0) >> ADDQ.L #$1,D2 ; 0(0/0/0) 2(0/0/0) 3(0/1/0) >> MOVE.L D2,i ; 3(0/0/1) 5(0/0/1) 7(0/1/1) > ;=6(1/0/1) 14(1/0/1) 19(1/4/1) >> i++; >> MOVE.L i,D2 ; 3(1/0/0) 7(1/0/0) 9(1/2/0) >> ADDQ.L #$1,i ; 3(0/0/1) 4(0/0/1) 6(0/1/1) ;+3(1/0/0) 5(1/0/0) 6(1/1/0) > ;=9(2/0/1) 16(2/0/1) 21(2/4/1) >> ++i; >> ADDQ.L #$1,i ; 3(0/0/1) 4(0/0/1) 6(0/1/1) ;+3(1/0/0) 5(1/0/0) 6(1/1/0) > ;=6(1/0/1) 9(1/0/1) 12(1/2/1) For the 68000, the numbers mean: Total Clock Cycles (Read Cycles/Write Cycles) Read Cycles and Write Cycles == 4 Clock Cycles. So, for example, 18(3/1) is 18 clock cycles, of which 12 (4*3) are read cycles, 4 (1*4) are write cycles, and the remainder (2) are cycles required for some internal function of the processor. The assumption that zero wait state memory is used isn't valid for all 68000 based Macintoshes; I can't remember which. For the 68020, the numbers mean: Total Clock Cycles (Read Cycles/Instuction Access Cycles/Write Cycles) Read, Write and Instruction Access Cycles == 3 Clock Cycles. The timings shown for the 68020 assume all operands are longword aligned, a 32-bit data bus, and zero wait state memory. Sorry, I don't have a 68030 manual. So, what does this all mean? 1. 68020s are faster than 68000s. 2. Knowing how fast anything runs on a 68020 is context dependant. 3. Running two instructions takes longer than running one of the two. 4. I'm a sucker when somebody says "Anybody got a manual?" :-) Cheers! -Eric -- Eric K. Olson, Editor, Prepare() NOTE: olson@bootsie.uucp will not work! Lexington Software Design Internet: olson@endor.harvard.edu 72A Lowell St., Lexington, MA 02173 Usenet: harvard!endor!olson (617) 863-9624 Bitnet: OLSON@HARVARD