Path: utzoo!attcan!utgpu!news-server.csri.toronto.edu!clyde.concordia.ca!thunder.mcrcim.mcgill.edu!snorkelwacker.mit.edu!apple!usc!zaphod.mps.ohio-state.edu!tut.cis.ohio-state.edu!att!bellcore!messy!mo From: mo@messy.bellcore.com (Michael O'Dell) Newsgroups: comp.arch Subject: Re: ECL SPARCs and FPS Message-ID: <1990Dec23.165517.8382@bellcore.bellcore.com> Date: 23 Dec 90 16:55:17 GMT Sender: usenet@bellcore.bellcore.com (Poster of News) Reply-To: mo@bellcore.com (Michael O'Dell) Organization: Center for Chaotic Repeatabilty Lines: 15 If I were a betting man, I'd wager that if FPS is building an ECL SPARC system, they are using the BIT ECL SPARC chips developed by Bipolar Integrated Technology (BIT) in conjunction with SUN. The parts were announced well over a year ago (over 18 months ago??) and were available before the MIPS ECL parts were announced, I believe. The BIT SPARC chips were designed for an 80 MHz clock, but if memory serves me right, only one chip in the set (fpu controller maybe???) goes that slowly (yes, that slowly!). I don't have the data sheets handy any more... Gee, I wonder if I know anybody who might be working on such a beast, and I wonder if they skulk around reading this newsgroup?? -Mike