Path: utzoo!utgpu!news-server.csri.toronto.edu!rutgers!usc!wuarchive!uunet!cbmvax!raible
From: raible@cbmvax.commodore.com (Bob Raible - LSI Design)
Newsgroups: comp.sys.amiga.hardware
Subject: Re: ECS chips????
Message-ID: <16803@cbmvax.commodore.com>
Date: 27 Dec 90 06:40:58 GMT
References: <1990Dec21.001727.20190@monu6.cc.monash.edu.au> <24188@grebyn.com>
Reply-To: raible@cbmvax.commodore.com (Bob Raible - LSI Design)
Organization: Commodore, West Chester, PA
Lines: 39

In article <24188@grebyn.com> ckp@grebyn.UUCP (Checkpoint Technologies) writes:
>In article <1990Dec21.001727.20190@monu6.cc.monash.edu.au> vac253v@monu6.cc.monash.edu.au (Richard Jones) writes:
>>I have seen a few specs on the ecs floating around this newsgroup, but I would  like to get it all in one place. Just a few q's....
>>
>>
>>1) Fatter agnus. I know I have one. I know it allows 1 Meg ChipRam.
>>Anything else?
>
>Bigger blits, up from 1K by 1K to 32K by 32K pixels.
>New DMA timing parameters to match the new Denise resolutions.
>
>>2) ECS Paula. what's it do?
>
>No such chip.  Paula is unchanged.
>
>>3) ECS Gary. does it exist. what's it do?
>
>Again, no such chip.
>
>>4) ECS Denise. what's it do?
>
>New Genlock/transparency modes
>Productivity mode (35ns pixel mode)
>Fully programmable horizontal and vertical resolutions
                                   ^^^^^^^^

	My lady-friend Denise has no knowledge of the vertical scheme of
	things. In fact she has to monitor bitplane activity to
	determine if she's within the bounds of the vertical display
	window as determined by AGNUS. This tends to illustrate that the
	chip partitioning causes some procedural difficulties.

	Other than this faux-pas, this description is fairly accurate. I
	posted something similar not to long ago.
>-- 
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