Path: utzoo!utgpu!news-server.csri.toronto.edu!rutgers!cs.utexas.edu!sdd.hp.com!ucsd!ucrmath!rhyde From: rhyde@ucrmath.ucr.edu (randy hyde) Newsgroups: comp.sys.apple2 Subject: Re: Multitasking on a II Message-ID: <10806@ucrmath.ucr.edu> Date: 29 Dec 90 06:20:50 GMT References: Organization: University of California, Riverside Lines: 27 >>> All 65x02 instructions are uninterruptible. This is true for the 65x02, but not the 65c816. The 65c816 as the /abort pin which can interrupt an instruction on any given clock cycle, not just an instruction fetch. As mentioned earlier, uninterruptible instructions don't stop DMA (e.g., multiple processors like a MILL, Softcard, or other coprocessor) from munging data between clock cycles. Why not just use the SEI instruction to prevent entrance into a critical section? On cheap systems you can do this. An error in the program (i.e., forgetting to turn the interrupts back on) could destroy the multitasking system though. >> Poorest interrupt latencies in the known market. Hmm.., let's see here. 7 cycles at 2.8Mhz is approx 2.5 usec. That's much better than a lot of processors. Furthermore, the 65xxx has a limited number of registers to save on an interrupt, meaning many fewer cycles pushing and popping registers. The 80x86, 68000, 32000, and RISC chips are the ones that have terrible interrupt latency times, not the 65xxx. Keep in mind, the 65xxx was designed as a controller chip-- it's supposed to be used in an interrupt driven environment. It handles interrupts rather well. Indeed, the 65xxx isn't a bad chip for fast interrupt response. It's just lacking certain features for a full general purpose preemptive multitasking OS (like memory management). *** Randy Hyde