Path: utzoo!mnetor!tmsoft!torsqnt!news-server.csri.toronto.edu!cs.utexas.edu!uunet!timbuk!cs.umn.edu!ux.acs!vx.acs.umn.edu!dhoyt From: dhoyt@vx.acs.umn.edu (DAVID HOYT) Newsgroups: comp.sys.mac.hardware Subject: Re: Memory speeds can be critical (was: SIMMs for IIsi - what do I need?) Message-ID: <2946@ux.acs.umn.edu> Date: 21 Dec 90 15:13:52 GMT References: <2915@ux.acs.umn.edu> <2924@ux.acs.umn.edu> Sender: news@ux.acs.umn.edu Reply-To: dhoyt@vx.acs.umn.edu Organization: University of Minnesota, Academic Computing Services Lines: 38 News-Software: VAX/VMS VNEWS 1.3-4 In article , amanda@visix.com (Amanda Walker) writes... > However, I still do not see how the speed of one SIMM can >affect the others in its bank, even with brain-dead driver circuitry. >I mean, if using all 100ns works, and using all 80ns works, how can >using two of each cause a problem. All of the SIMMs are still within >tolerances--just in different places within them. It's a matter of how much difference in speed (and other electrical) differences the memory drivers can handle. Each chip is unlikely to have exactly the same characteristics as the other chips. Memory drivers are designed to compensate for these differences as long as they are small. Now each bank of memory has its own driver circuitry, so each bank can handle separate ranges of variations (++++ vs ----). Variation between banks is then adjusted so the entire memory subsystem looks to be the same. This is why you can get by with a bit more differences between banks than within banks. >We're not talking putting bipolar SIMMs (an amusing concept) into a IIsi. Okay, so I cheated. Bipolar chips would either be blown by or blow the memory drivers. > A 100ns SIMM may well be an 80ns SIMM that got marked >as 100ns because the memory company had more orders for 100ns SIMMs that >month. The rating is simply the worst case--the best case is always >undefined. In the micro market place the best case might be undefined (because nobody knows to ask) but the real world the best case is designated as well. When Cray builds a 256 Megaword (call it 2GB in the micro world) Cray 2 you better believe that it specifies both the best and the worst case for those chips. If the memory supplier 'slipped' in a few 60ns chips along with the trainload of 80ns chips it could render the $20 million machine useless. It would probably cause sporadic memory errors at the very best. The reason that we can get by with it in our micros is that the micros don't have the complexity that turns lots of little differences into one big, unworkable difference. david | dhoyt@vx.acs.umn.edu | dhoyt@vx.acs.umn.edu