Path: utzoo!mnetor!tmsoft!torsqnt!news-server.csri.toronto.edu!cs.utexas.edu!usc!apple!bionet!ames!eos!shelby!neon!kaufman From: kaufman@Neon.Stanford.EDU (Marc T. Kaufman) Newsgroups: comp.sys.mac.hardware Subject: Re: Memory speeds can be critical (was: SIMMs for IIsi - what do I need?) Message-ID: <1990Dec21.152257.20969@Neon.Stanford.EDU> Date: 21 Dec 90 15:22:57 GMT References: <2924@ux.acs.umn.edu> Organization: Computer Science Department, Stanford University Lines: 14 In article n67786@lehtori.tut.fi (Nieminen Tero) writes: >Only reason for this I can think of is that the logic doesn't properly >check the memory ready lines from all simms in a bank but instead just >uses one single sim for that purpose... That would be a good argument, IF there were "memory-ready" lines from the simms... but there are no such lines. Simm timing is strictly controlled by external circuitry waiting for the prescribed times. Tell me, how did you think of that reason? What data book or hardware reference has it? Marc Kaufman (kaufman@Neon.stanford.edu)