Path: utzoo!mnetor!tmsoft!torsqnt!news-server.csri.toronto.edu!clyde.concordia.ca!thunder.mcrcim.mcgill.edu!snorkelwacker.mit.edu!mit-eddie!uw-beaver!cornell!rochester!kodak!uupsi!sunic!news.funet.fi!cc.tut.fi!assari.tut.fi!n67786 From: n67786@lehtori.tut.fi (Nieminen Tero) Newsgroups: comp.sys.mac.hardware Subject: Re: Memory speeds can be critical (was: SIMMs for IIsi - what do I need?) Message-ID: Date: 22 Dec 90 17:50:08 GMT References: <2924@ux.acs.umn.edu> Sender: n67786@cc.tut.fi (Nieminen Tero) Organization: Tampere Univ. of Technology, Finland. Lines: 31 In-Reply-To: amanda@visix.com's message of 21 Dec 90 17:34:47 GMT In article amanda@visix.com (Amanda Walker) writes: In article n67786@lehtori.tut.fi (Nieminen Tero) writes: >Only reason for this I can think of is that the logic doesn't properly >check the memory ready lines from all simms in a bank but instead just >uses one single sim for that purpose. This would be a perfect explanation except for one problem: SIMMs don't have "memory ready" lines, or any kind of strobe or signal that indicates when the data is ready. It's the driver circuit's responsibility to wait long enough. This is why, for example, you can't use cheaper but slower SIMMs than a machine is rated for--the driver logic will assume the data is ready, even if it's not, because there is no way for it to tell. Ok. My knowledge was outdated to the times of static memories :). Thanks for the update. If this is the case one would appear to be playing russian roulette with fully loaded revolver, eh. Maybe the machines just have enough wait states to compensate.. BTW, it's often not possible to use slow rams on systems that have memory ready signal, cause the cpu don't know how to wait. -- Amanda Walker amanda@visix.com Visix Software Inc. ...!uunet!visix!amanda -- Black holes are where God is dividing by zero. -- Tero Nieminen Tampere University of Technology n67786@cc.tut.fi Tampere, Finland, Europe