Path: utzoo!mnetor!tmsoft!torsqnt!news-server.csri.toronto.edu!clyde.concordia.ca!thunder.mcrcim.mcgill.edu!snorkelwacker.mit.edu!apple!agate!shelby!neon!kaufman From: kaufman@Neon.Stanford.EDU (Marc T. Kaufman) Newsgroups: comp.sys.mac.hardware Subject: Re: Memory speeds can be critical (was: SIMMs for IIsi - what do I need?) Message-ID: <1990Dec23.175856.22531@Neon.Stanford.EDU> Date: 23 Dec 90 17:58:56 GMT References: Organization: Computer Science Department, Stanford University Lines: 24 -(Nieminen Tero) writes: ->Only reason for this I can think of is that the logic doesn't properly ->check the memory ready lines from all simms in a bank but instead just ->uses one single sim for that purpose. >(Amanda Walker [one of many]) replies: > This would be a perfect explanation except for one problem: SIMMs > don't have "memory ready" lines, or any kind of strobe or signal that > indicates when the data is ready. ->then (Nieminen Tero) writes: ->Ok. My knowledge was outdated to the times of static memories :). Uh... Nieminen.... static memories don't have ready lines either. ->BTW, it's often not possible to use slow rams on systems that have ->memory ready signal, cause the cpu don't know how to wait. The only memory systems (not individual chips) I know of with "ready" lines are those interfaced to a bus structure, such as NuBus, VME or Versabus, etc. In all of these I am aware of, waiting for ready is a mandatory part of the bus protocol. Marc Kaufman (kaufman@Neon.stanford.edu)