Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!uunet!fernwood!portal!apple!north From: north@Apple.COM (Don North) Newsgroups: comp.sys.mac.hardware Subject: Re: Memory speeds can be critical (was: SIMMs for IIsi - what do I need?) Message-ID: <47604@apple.Apple.COM> Date: 27 Dec 90 20:45:19 GMT References: <2915@ux.acs.umn.edu> Organization: Apple Computer, Inc. Lines: 49 In article amanda@visix.com (Amanda Walker) writes: >All right, now I'm really confused, and I've built DRAM circuitry... >In article <2915@ux.acs.umn.edu> dhoyt@vx.acs.umn.edu writes: >> >>Imagine you have a chip that is rated at 120ns with a 120ns driver. >>(Greatly simplifying) you will have a signal that looks like this >> +---+ +---+ >> | | | | >> ----+ +-----------------------+ +---------------------- >> 0 ns Time-> 120ns >> >>I.e. the amount of time that the signal takes to get through the chip is >>roughly 120ns. >> >Not even close. There is no signal "going through the chip." The >"speed" of a dynamic RAM which is usually quoted (and which is printed >on the chip) is not a propagation delay. It is the Row Access Time, > >Once again, the Mac can't tell when the data is ready; it just waits >the rated amount of time and latches the data then. If the outputs >settle 20ns early, it doesn't care. They'll still be there until it >gets done with them. Amanda is right; no if's and's or but's! There is no reason why SIMM speeds cannot be mixed as long as they meet the maximum access time spec'ed for the particular machine (ie, 120ns or 100ns or 80ns). Think about it; on a given SIMM there are EIGHT individual memory chips built from EIGHT individual pieces of silicon (they don't even have to be from the same manufacturer, but usually are) - those eight chips are certainly not matched down to the nearest nanosecond in their access times. In fact one could conceivably build a SIMM with a mixture of 80ns,100ns,120ns parts and call it a '120ns' SIMM. If TN176 says that SIMM speeds cannot be mixed then it is WRONG - as long as all the SIMMs meet or exceed (are faster) the required access time spec. I am intimately familiar with the various Mac memory interface circuits and have built numerous other DRAM controllers, and there is NO REASON why DRAM speeds cannot be mixed - as long as the required maximum access time is met. Remember, whenever you have more than ONE DRAM in a circuit you are mixing speeds! -- Don North ----- Apple Computer, Inc. ----- Advanced Technology Group UUCP: ...!{voder,nsc,decwrl,sun}!apple!north CSNET: north@Apple.COM {{ Facts are facts, but any opinions expressed are my own, and *do not* }} {{ represent any viewpoint, official or otherwise, of Apple Computer, Inc.}}