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From: touch@dsl.cis.upenn.edu (Joe Touch)
Newsgroups: sci.electronics
Subject: game arbitrator
Message-ID: <34827@netnews.upenn.edu>
Date: 15 Dec 90 17:12:03 GMT
Sender: news@netnews.upenn.edu
Reply-To: touch@dsl.cis.upenn.edu (Joe Touch)
Organization: University of Pennsylvania
Lines: 45



RS-latches?  JK-flip flops?  A whole C-64?  Geez, folks, talk about
doing things the hard way!!

Here's a way thats SIMPLE, CHEAP, AND *SCALABLE* (easy to extend to an
arbitrary number of inputs, if you balance the OR into balanced trees)

It also has the advantage of a 3-gate propagation delay for latch, so
it will lock out ties unless they come within 3 gate times of each
other (about 25 ns for TTL).  That is a smaller 'false tie' window
than RS/JK solutions will give! I'm not sure if debouncing is
required at the inputs - if they are stable for the setup time of 
the feedback loop (i.e. if a bouncy switch still outputs at least
a pulse of 25ns), debouncing can be avoided.

                              +-----+
     in1    ------------------| D-  |--------+-------- out 1
     in2    ------------------|latch|--------|-+------ out 2
     in3    ------------------|     |--------|-|-+---- out 3
     in4    ------------------|     |--------|-|-|-+-- out 4
                              +--^--+        | | | |
                                 |           | | | |
                               +-+---+     +-+-+-+-+-+
                               | AND |     |   OR    |
                               +-+-+-+     +----+----+
                                 | |            |
 reset-bar ----------------------+ +------------+

When reset-bar is low (reset) the clock of the D latch is LOW,
passing all data through. When reset-bar is high, all data passes 
through.

If any input goes high, the OR goes high, the latch gets locked,
and a feedback loop exists, locking the outputs.

Any number of D-latches can be used, provided that the OR tree is
balanced, it will be fair.

Occam's Razor lives - look for the simple solution.

Joe Touch
PhD Candidate
Dept of Computer and Information Science
Univ of Pennsylvania