Path: utzoo!utgpu!news-server.csri.toronto.edu!rutgers!apple!baum From: baum@Apple.COM (Allen J. Baum) Newsgroups: comp.arch Subject: Re: more registers for ix86, was: Let's pretend Message-ID: <47790@apple.Apple.COM> Date: 6 Jan 91 05:57:34 GMT References: <9854@as0c.sei.cmu.edu> Reply-To: baum@apple.UUCP (Allen Baum) Organization: Apple Computer, Inc. Lines: 33 [] >In article qzhe1@cs.aukuni.ac.nz (Qun Zheng ) writes: >Is there a modern processor without registers? If there is, how do they catch >up the speed, playing which sort tricks on caches? The only one I'm aware of is the ATT CRISP, which is a mem-mem architecture. The only address modes are: immed, SP-relative, indirect SP-relative, and absolute (? could be wrong here...PC-rel also?). By caching the top of stack (i.e., the first 32 locs relative to the SP) in an extremely small, dual ported cache, these references look more like register references, even needed only five bits in the instruction to reference them. Unlike the usual cache tag mechanism, there is a bounds check, since the top of stack must be contiguous. In addition, they don't allocate on a miss- special instructions allocate and deallocate (on procedure entry/exit). In that sense, it looks like register windows with variable size windows. So, its sorta like registers, except that it goes to mem if you access something else. Needless to say, generally the absolute and indirect modes will miss. ALSO it will go to the registers if you access them through a pointer! That means you don't have to worry about making sure a variable is in memory if you might have a pointer to it. For example, an interrupt merely changes the SP. All references then miss, and it starts running slow, unless the SP gets restored long enough to save the "registers"- but you don't have to save anything if you don't want to. -- baum@apple.com (408)974-3385 {decwrl,hplabs}!amdahl!apple!baum