Path: utzoo!censor!geac!torsqnt!news-server.csri.toronto.edu!clyde.concordia.ca!thunder.mcrcim.mcgill.edu!snorkelwacker.mit.edu!apple!baum From: baum@Apple.COM (Allen J. Baum) Newsgroups: comp.arch Subject: Re: more registers for ix86, was: Let's pretend Message-ID: <47789@apple.Apple.COM> Date: 6 Jan 91 05:42:37 GMT References: <5827@labtam.labtam.oz> <1991Jan6.014925.10935@zoo.toronto.edu> Reply-To: baum@apple.UUCP (Allen Baum) Organization: Apple Computer, Inc. Lines: 42 [] >In article <1991Jan6.014925.10935@zoo.toronto.edu> henry@zoo.toronto.edu (Henry Spencer) writes: --a nice summary of why registers win-- The reason that caches are used is because memory management is -hard to do -a pain in the ass -best done with run time info When these are not an issue, then it can be done extremely efficiently by the programmer. Lo and behold, for very small amounts of memory (like <32 variables), the programmer still has problems, but some other program (the compiler) can manage it. Hence, registers are extremely. In general, memory addresses are much bigger than register references, but in particular they don't have to be, e.g. CRISP which uses a small offset from some pointer. As has been pointed out in the past, registers are the top of the memory hierarchy. The characteristics that make it different than those other levels: multiple ports, sub-cycle access, and extremely small size. (generally speaking, of course) >> Speaking of caches, I seem to recall that single-storage-area caches >>are supposed to be more efficient than caches which have separate >>areas for different things... > >Again, "more efficient" in what sense? Current experience strongly points >to the reverse, at least for the obvious case of instructions vs. data. >Splitting a cache loses the ability to use any free space to fulfill a new >request, but gains the ability to specialize the hardware and parallelize >data paths. In the sense that 1 unified cache will have a better hit ratio than seperate I/D caches of half the size each, yes, it is more efficient. However, hit ratio is not everything. The performance gained by having split caches be accessed in parallel more than makes up for the fairly small loss due to extra misses. -- baum@apple.com (408)974-3385 {decwrl,hplabs}!amdahl!apple!baum