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From: scott@labtam.labtam.oz (Scott Colwell)
Newsgroups: comp.arch
Subject: Re: more registers for ix86, was: Let's pretend
Message-ID: <5833@labtam.labtam.oz>
Date: 7 Jan 91 00:31:19 GMT
References: <3042@crdos1.crd.ge.COM> <1990Dec26.020034.4131@lpi.liant.com> <5827@labtam.labtam.oz> <47713@apple.Apple.COM>
Organization: Labtam Australia, Melbourne, Australia
Lines: 42

baum@Apple.COM (Allen J. Baum) writes:
>>In article <5827@labtam.labtam.oz> scott@labtam.labtam.oz (Scott Colwell) writes:
>>On the 486, reg to reg operations take one clock, cached memory to reg take
>>two and reg to cached mem take three. By improving this performance and making
>>some changes to the cache allocation scheme, cache can and does compensate
>>for the lack of general purpose registers.

>I'm afraid that I can't let this statement of fact go unchallenged.
>I'm assuming it is fact- I have no reason to believe otherwise.

Thankyou ;-)

>For example, it is easy to make a memory (or cache) access a single single
>if you make your cycle slow enough.
..
>Secondly, you can make horribly complicated instructions take a single
>cycle (even for fast cycles) if you make your pipeline deep enough.
>Unfortunately, deep pipes have a problem with stalling because of branches and
>dependencies when the pipeline gets deep.
..

I accept that all these are valid comments but again using the example
of the 486, Intel have come up with an implimentation that goes quickly.
It appears to have integer performance comparable to many of the RISC
processors (although not up with the faster ones.) If we accept that the
486 at 33MHz has around 15 vax mips (Intel's quoted integer spec is 17.6
Nov/Dec 1990 issue of Solutions,) then we get somewhere around 2.2 'vax
instructions' per clock.

I hate to appear to be supporting a less than perfect architecture but
for Intel, the name of the game is not to make a fast microprocessor
but to make the fastest x86 compatible processor. In this context, I think
that Intel have made good design tradeoffs. Imagine what might be produced if
the silicon technology and the effort that are put into the x86 and 860
groups was put into just one RISC family rather than the two RISC and one
CISC family that Intel have today. (i.e. x86, 860, 960)

-- 
Scott Colwell
Senior Design Engineer
Labtam Australia		net:	scott@labtam.oz.au
Melbourne, Australia 		phone:	+61-3-587-1444