Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!usc!julius.cs.uiuc.edu!apple!baum
From: baum@Apple.COM (Allen J. Baum)
Newsgroups: comp.arch
Subject: Re: more registers for ix86, was: Let's pretend
Message-ID: <47822@apple.Apple.COM>
Date: 7 Jan 91 20:10:03 GMT
References: <5827@labtam.labtam.oz> <47713@apple.Apple.COM> <5833@labtam.labtam.oz>
Reply-To: baum@apple.UUCP (Allen Baum)
Organization: Apple Computer, Inc.
Lines: 19

[]
>In article <5833@labtam.labtam.oz> scott@labtam.labtam.oz (Scott Colwell) writes:
--my comments on using cache as a substitute for more regs--
>
>I hate to appear to be supporting a less than perfect architecture but
>for Intel, the name of the game is not to make a fast microprocessor
>but to make the fastest x86 compatible processor. In this context, I think
>that Intel have made good design tradeoffs.

Well, we may be on the same side. Given the 80x86 ISA, then what Intel did
might be the best solution.

What I was arguing was that cache is not a substitute for more regs., although
marketing benchmarks and numbers might make it appear so.


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