Newsgroups: comp.archives Path: utzoo!utgpu!news-server.csri.toronto.edu!ox.com!emv From: naumann@acsu.buffalo.edu (Dirk Naumann) Subject: [comp.arch] References on asynchronous design Message-ID: <1991Jan6.202520.10029@ox.com> Followup-To: comp.arch Sender: emv@ox.com (Edward Vielmetti) Reply-To: naumann@acsu.buffalo.edu (Dirk Naumann) Organization: SUNY Buffalo References: <53594@eerie.acsu.Buffalo.EDU> Date: Sun, 6 Jan 91 20:25:20 GMT Approved: emv@ox.com (Edward Vielmetti) X-Original-Newsgroups: comp.arch Archive-name: lsi/design/async-tr/1991-01-06 Archive: cs.utah.edu:/pub/async-tr-90-016.ps.Z [128.110.4.21] Original-posting-by: naumann@acsu.buffalo.edu (Dirk Naumann) Original-subject: References on asynchronous design Reposted-by: emv@ox.com (Edward Vielmetti) Since I could reply to everyone who sent me mail asking for references, I'll post it here. Following is the original posting from the university of Utah. Martins approach is best described in "Programming in VLSI: From Communicating Processes to Delay-Insensitive Circuits", to appear: UT Year of Programming Istitute on Concurrent Programming, C.A.R. Hoare, editor; Addison-Wesley, 1990 Hope it helps. Dirk ------------------------------------------------------ Article: 1260 of comp.lsi Path: ub!zaphod.mps.ohio-state.edu!usc!ucsd!dog.ee.lbl.gov!hellgate.utah.edu!bli ss.utah.edu!ganesh From: ganesh%bliss.utah.edu@cs.utah.edu (Ganesh C. Gopalakrishnan) Newsgroups: comp.lsi Subject: Asynchronous system / "self-clocked" design - a survey TR available Message-ID: <1990Oct7.214127.10262@hellgate.utah.edu> Date: 8 Oct 90 03:41:26 GMT Organization: Dept of CS, U of U Lines: 69 There was a recent enquiry regarding asynchronous system ("self-clocked circuit") design in this newsgroup. If you are interested, myself and a student of mine have surveyed some of the work in this area, in a tech. report. You may FTP a postscript file containing this report. (Note: this report will occasionally be updated to fix errors.) ------------------------------------------------------- "Some Recent Asynchronous System Design Methodologies" by Ganesh Gopalakrishnan (ganesh@cs.utah.edu) Prabhat Jain (jain@cs.utah.edu) Technical Report Number UU-CS-TR-90-016, Department of Computer Science, University of Utah, October 1990, 55 pages ABSTRACT We present an in-depth study of some recent techniques for asynchronous system design, analysis, and verification. After defining basic terminology, we take one simple example---a four-phase to two-phase converter---and present its design using classical flow-tables, Signal Transition Graphs of Chu, and Trace Theory of Ebergen. We then present necessary and sufficient conditions for Delay Insensitivity, proposed by Udding, and illustrate it on our example. Finally, we present the work of Dill on the verification of asynchronous circuits, and illustrate it on the circuits derived in the paper. The following points are emphasized: (i) presentation of techniques at more depth than in a general survey; (ii) illustration of all the aspects discussed on a common example; (iii) comparative study of the works presented. Many interesting works had to be left out, solely because of our lack of space and time. ---- You may FTP a compressed postscript file of this techreport. FTP instructions: ftp open cs.utah.edu login: anonymous password: guest binary cd pub get async-tr-90-016.ps.Z close bye Then uncompress async-tr-90-016.ps.Z lpr -P async-tr-90-016.ps Please also send mail to ganesh@cs.utah.edu, and let me know (for my own records) your name, postal address, and email address. ---- Comments are most welcome. Cheers, Ganesh @ cs.utah.edu -- Dirk Naumann naumann@eng.buffalo.edu, ECE Department, SUNY at Buffalo