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From: naumann@autarch.acsu.buffalo.edu (Dirk Naumann)
Newsgroups: comp.lsi,comp.lsi.cad
Subject: SIS logic optimizer
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Date: 7 Jan 91 17:13:02 GMT
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Does anybody know the stage of development of the logic optimizer
SIS, which is supposed to do logic circuit optimization for
sequential circuits ?

Thanks in advance

-- 
Dirk Naumann
naumann@eng.buffalo.edu, ECE Department, SUNY at Buffalo