Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!uunet!mcsun!ukc!acorn!asmith
From: asmith@acorn.co.uk (Andy Smith)
Newsgroups: comp.sys.acorn
Subject: Re: ARM4
Message-ID: <4576@acorn.co.uk>
Date: 2 Jan 91 18:42:05 GMT
Sender: asmith@acorn.co.uk
Distribution: comp
Organization: Acorn Computers Ltd, Cambridge, England
Lines: 73

References: <1990Dec28.135619.21679@odin.diku.dk>
Distribution: comp
Organization: Acorn Computers Ltd, Cambridge, England

In article <1990Dec28.135619.21679@odin.diku.dk> torbenm@diku.dk (Torben [gidius Mogensen) writes:

>I *know* nothing about the developments of an ARM4, but I have some
>guesses. Acorn announced that a FPU would be available for the new
>workstation series, so I expect this to be one of the first new
>products that ARM Ltd. will produce.

There will be a new ARM, but I doubt that it will be called ARM4. The FPA is
mentioned in the A540 and the R260 literature, so should appear later this year.

>Also, given the fact that the 4-chip set used in A3000 and A400
>contains a smaller number of transistors combined than for example
>Intel 386 or Motorola 68030, I would expect a single-chip version of
>that set (ARM2, MEMC, VIDC & IOC) to be produced. This could be used
>to make low cost machines (a cheaper A3000?). This would be similar to
>the chip used in the Active Book.

I have been informed that it would be cheaper to put all four of the ARM
chip set onto one piece of silicon, though I doubt that this will be done,
as there are more viable things for ARM ltd to do. Think of it this way;
would anyone want it other than Acorn, and would they redesign the
Archimedes to take it, considering the new ARM's in the pipeline?

>A variant of this with an ARM3 and FPU would be a logical next step.

Why?? 

>Also, I expect improved versions of MEMC and VIDC to be produced. The
>fact that MEMC only have 128 pages has always been one of the great
>limiting factors in the ARM design. A MEMC with 512 or 1024 pages
>would be essential for high end machines. A new VIDC could be equipped
>with a larger colour table (256 entries) and the possibility of doing
>direct mapped 15 or 30 bit RGB. The numbers 15 and 30 seem logical, as
>they fit into 16 or 32 bit words, continuing the present bit-doubling
>strategy. Even if not all bits are sent to the DACs, 15 and 30 bit
>formats seems like good aiming points.

The following is taken from a paper by J.P. Biggs & P.L. Harrod:-

BOUNDARY SCAN DESIGN FOR A MEMORY CONTROLLER

A boundary-scan design that fully conforms to the IEEE 1149.1 standard has been incorporated in 
MEMC2, a complete memory and system controller for ARM-based systems. MEMC2 provides a 
two level memory management system: Level 1 Page Tables are stored on-chip for improved 
access speed while the larger Level 2 Tables are stored in main memory. An on-chip 64-entry 
Translation Lookaside Buffer of Level 2 Page Tables further improves performance by caching 
most recently used translations. The chip can control a large DRAM memory system; it also 
provides support for static RAM and ROM and provides a video interface and seven on-chip DMA 
channels. This device has recently been fabricated by VLSI Technology in their 1.05m double-level 
metal CMOS process and it is fully functional.

The paper is about using boundary scan, but includes information on MEMC 2,
which already exists. As for other chips, thats now upto ARM ltd.

>As for other manufacturing techniques, I think that it is too early to
>aim for ECL, bipolar or GaAs. Low power CMOS versions (like used in
>the Active Book) seems more propable.

There is a CMOS version of the ARM, as used in the ABC, I doubt that the
other technologies will be used until they are cost effective. The whole
idea of ARM is to offer fantastic price/performance, something other RISC
processors fail to do. 

>
>	Torben Mogensen (torbenm@diku.dk)
                       
Andy

The views expressed here are completely my own.