Path: utzoo!utgpu!news-server.csri.toronto.edu!rutgers!cbmvax!raible
From: raible@cbmvax.commodore.com (Bob Raible - LSI Design)
Newsgroups: comp.sys.amiga
Subject: Re: Commodore Research and Development.
Message-ID: <17160@cbmvax.commodore.com>
Date: 7 Jan 91 04:32:01 GMT
References: <1991Jan3.003449.1@ccvax.iastate.edu> <17114@cbmvax.commodore.com> <75723@unix.cis.pitt.edu>
Reply-To: raible@cbmvax.commodore.com (Bob Raible - LSI Design)
Organization: Commodore, West Chester, PA
Lines: 34

In article <75723@unix.cis.pitt.edu> sjcst2@unix.cis.pitt.edu (Scott J. Corley) writes:
>Dave , does this mean that we wont see SVGA resolution graphics on the
>next generation of the Amiga chipset because it has to stay compatible
>with the 15.75kHz scan rate of NTSC and getting SVGA resolution 
>requires a higher scan rate? I hope this isnt true. Even if Commodore
>or some 3rd party company comes out with a FlickerFixer for a high 
>resolution NTSC compatible mode , it still isnt as good as having a
>high scan rate built in. I have a A3000 and I hate it when you move
>things on the screen and you get a double image because of the 
>built in FlickerFixer. Its really annoying when reading text.
>
>
>               Scott Corley

I'm not even related to Dave H. but I'll answer for the simple reason
that I'm responsible for ECS Denise and am working on stuff that
directly relates to your question(I hope that's sufficiently vague :3).
Currently, the Amiga chip set is synchronized to the NTSC color clock
and incidentally the chip memory bus cycle. This results in pixel clock
rates of 7,14,and 28MHZ in the latest chip set(ECS as found in A3000).
Scan rate is totally programmable in these chips and higher scan rates
are easy to configure. I assume by SVGA you refer to the 35KHZ scan
rate, 1000x768 screen variety(literature I've seen refers to several
screen formats under the heading of SVGA). In this case the pixel clock
required to fill the screen is about 36MHZ. This is not equal to the
color clock multiplied by a power of two and would require changing the
system clock rate or uncoupling the system clock from the pixel clock.
Both require major architectural changes to the custom chip set. Far
easier would be to offer 56MHZ pixels(28MHZ x 2). As I said scan rate
would be programmable by the application(50KHZ or so I presume). This
is within the display range of a lot of multisync monitors.

PS: pls note that 31KHZ is already offered in 3000,your statement seems
to imply 15KHZ is current limit.