Path: utzoo!utgpu!news-server.csri.toronto.edu!rutgers!mcnc!uvaarpa!murdoch!batik.cs.Virginia.EDU!sam2y
From: sam2y@batik.cs.Virginia.EDU (Steven A. Moyer)
Newsgroups: comp.sys.intel
Subject: Cache line reads for the i860
Message-ID: <1991Jan5.154331@batik.cs.Virginia.EDU>
Date: 5 Jan 91 20:43:31 GMT
Sender: news@murdoch.acc.Virginia.EDU
Reply-To: sam2y@batik.cs.Virginia.EDU (Steven A. Moyer)
Distribution: usa
Organization: University of Virginia
Lines: 23


--
I'm looking for information concerning how cache lines are filled on the
i860 processor.  In particular, does the i860 make use of the NA# signal
(assuming it is support by the memory subsystem) in order to pipeline
cache line reads?

In measuring load rates on an RX node, I can obtain a rate of 20M/sec
using the pfld instruction.  With the cache flushed so that there is
no write-back, I can only obtain a rate of 10M/sec using the fld
instruction.  Yet, the hardware reference manual seems to imply that the
cache controler does indeed take advantage of memory pipelining when
available.

Any ideas?


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| Steven Moyer                   |       THIS SPACE FOR RENT         |
| University of Virginia         |                                   |
|                                | "Just a rebel without a clue..."  |
| E-mail: sam2y@virginia.edu     |                - The Replacements |
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