Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!swrinde!zaphod.mps.ohio-state.edu!mips!hal!mark From: mark@mips.COM (Mark G. Johnson) Newsgroups: comp.arch Subject: Re: Asynchronous Microprocessors Message-ID: <44601@mips.mips.COM> Date: 8 Jan 91 14:54:03 GMT References: Sender: news@mips.COM Lines: 32 > >Can anybody suggest any suitable references, or research groups >working in this area > Abbreviated Abstract: [emphasis mine] "Self-timing *introducing no delay overhead* controls a 7mm2 iterating ring for mantissa computation of floating-point division. The datapath has embedded completion encoding *and no latches*. Quotients and done indication appear in 45 to 160ns, depending on data operands. Implementation is in 1.2 um CMOS technology." Parenthetical Note: [mine] Present generation RISCs use 0.8 um CMOS technology (considerably better than 1.2 um) and achieve divide times of 300 - 700ns [Hennessey and Patterson page A-53]. They include, of course, the additional overhead of exponent calculations. Citation: Ted Williams and Mark Horowitz, "A Zero-Overhead Self Timed 160ns 54bit CMOS Divider," paper 5.5, IEEE International Solid State Circuits Conference (ISSCC), February 14, 1991, San Francisco. -- -- Mark Johnson MIPS Computer Systems, 930 E. Arques M/S 2-02, Sunnyvale, CA 94086 (408) 524-8308 mark@mips.com {or ...!decwrl!mips!mark}