Path: utzoo!utgpu!news-server.csri.toronto.edu!bonnie.concordia.ca!thunder.mcrcim.mcgill.edu!snorkelwacker.mit.edu!think.com!spool2.mu.edu!uunet!mcsun!ukc!edcastle!cs.ed.ac.uk!cs.edinburgh.ac.uk!ddr From: ddr@cs.edinburgh.ac.uk (Doug Rogers) Newsgroups: comp.arch Subject: How about CACHE based registers, was: more registers for ix86 Message-ID: <4300@skye.cs.ed.ac.uk> Date: 10 Jan 91 11:40:36 GMT References: <5827@labtam.labtam.oz> <1991Jan6.014925.10935@zoo.toronto.edu> <47789@apple.Apple.COM> Sender: nnews@cs.ed.ac.uk Reply-To: ddr@cs.edinburgh.ac.uk (Doug Rogers) Organization: Department of Computer Science, University of Edinburgh Lines: 28 > > --a nice summary of why registers win-- > The reason that caches are used is because memory management is > -hard to do > -a pain in the ass > -best done with run time info The same applies to register allocation, where memory mapped registers could provide increased flexibility. Functional programmes are notoriously difficult to compile so that they use the registers efficiently so the abilty to use cache based registers is extremely attractive. This would provides the `register windowing' features automatically and allow a variable size of register set to suit the situation. The advantage of registers is however their multi-port capability allowing registers to be written to and read from within the same clock cycle. Typical super-serial designs are now using upwards of 5 ports. However even dual porting is worthwhile ( you can build a rather nice one-operand machine in this way using an accumulator and a large array of general purpose registers, this actually likes data dependancy to increase speed.) So therefore why not a special purpose multi port cache? I realise that there would be a problem with the speed of the associated memory, but because of the localised nature of access it should be possible to minimise the time delay due to this. -- Douglas Rogers JANET: ddr@uk.ac.ed.lfcs Department of Computer Science UUCP: ..!mcvax!ukc!lfcs!ddr University of Edinburgh ARPA: ddr%lfcs.ed.ac.uk@nsfnet-relay.ac.uk Edinburgh EH9 3JZ, UK. Tel: 031-650 5172 (direct line)