Path: utzoo!censor!geac!torsqnt!lethe!yunexus!ists!helios.physics.utoronto.ca!news-server.csri.toronto.edu!bonnie.concordia.ca!thunder.mcrcim.mcgill.edu!snorkelwacker.mit.edu!apple!baum
From: baum@Apple.COM (Allen J. Baum)
Newsgroups: comp.arch
Subject: Re: How about CACHE based registers, was: more registers for ix86
Message-ID: <47986@apple.Apple.COM>
Date: 11 Jan 91 19:03:04 GMT
References: <1991Jan6.014925.10935@zoo.toronto.edu> <47789@apple.Apple.COM> <4300@skye.cs.ed.ac.uk>
Reply-To: baum@apple.UUCP (Allen Baum)
Organization: Apple Computer, Inc.
Lines: 30

[]
>In article <4300@skye.cs.ed.ac.uk> ddr@cs.edinburgh.ac.uk (Doug Rogers) writes:
I said ... some reasons that caches are used is because mem management is hard

>The same applies to register allocation, where memory mapped registers
>could provide increased flexibility..

Yes, but my point was that reg. allocation has a known solution- we know
how to do it automagically, so we build processors that take that fact into
account.

>> Functional programmes are notoriously difficult to compile so that
>>they use the registers efficiently so the abilty to use cache based
>>registers is extremely attractive.

I probably should have said something to the effect that our
compilation abilities are highly developed in the areas of procedural
languages, and our mainstream applications and architecture
development are lead in those directions.

It is not clear to me that cache based register are a win. They might be,
but it not clear, and I have heard counterexamples.

>The advantage of registers is however their multi-port capability..

The ATT CRISP uses essentially a multi-ported cache for their 'registers'

--
		  baum@apple.com		(408)974-3385
{decwrl,hplabs}!amdahl!apple!baum