Path: utzoo!utgpu!news-server.csri.toronto.edu!bonnie.concordia.ca!uunet!fernwood!synopsys!craig From: craig@synopsys.com (Craig Cochran) Newsgroups: comp.lang.vhdl Subject: Re: VHDL and performance evaluation? (repost) Message-ID: <629@synopsys.COM> Date: 14 Jan 91 18:11:55 GMT References: <2924@laura.UUCP> <1991Jan12.174847.1116@hoss.unl.edu> Sender: news@synopsys.com Organization: Synopsys Inc. Lines: 26 In article <1991Jan12.174847.1116@hoss.unl.edu> savel@hoss.unl.edu (Bharat P. Savel) writes: > >above all, all these books teach VHDL, none really show how to use VHDL in >a layman's language; worse still, simulation of an entity is explained >(kind of) only in #1; it is shown in #2; NONE of the books mention how to >compile a entity ( like vhdl [filename]; THEN mg [filename]; THEN ......) >they assume that the manuals take care of that, the manuals themselves are >not well documented ( i have had atleast 2 other persons admitting that) >even more the VHDL hotline ( 1-800 number) is not manned; > The steps taken to simulate a configuration are not part of the IEEE 1076 specification (or any other industry standard), and therefore will vary wildly between products from different companies. From your description above, it sounds as if you are using the Intermetrics toolset, which, prior to being acquired by Valid, was command-line based. By contrast, an example is Vantage, who provides a graphical interface with no command-line compiler or model generator. Thus, these steps will have to be excluded from any generic book on VHDL modelling, as they are not applicable to VHDL users at large. -- Craig Cochran Product Marketing Manager email: craig@synopsys.com Synopsys, Inc. voice: (415)962-7723