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From: tcd@vax5.cit.cornell.edu
Newsgroups: comp.sys.m68k
Subject: inst. cache/optimization
Message-ID: <1991Jan10.104609.1939@vax5.cit.cornell.edu>
Date: 10 Jan 91 14:46:09 GMT
Distribution: comp
Lines: 16


     This is probably a dumb question and I'm not sure if this is the most
appopriate group, but here goes anyway.  Suppose one is writing an assembly
language program for a Macintosh with 68020/68881 chips that has a loop
containing just enough instructions to fill the instruction cache twice.
It seems that one would then get zero cache hits.  Would it make sense to
set the Freeze Cache bit halfway through the loop, or do something similar
with the Cache Control Register?  In a similar vein, unrolling loops is
suggested as a way to improve performance, but is this still likely to be
a good idea if, say, the original version just fills the instruction cache?
     I have spent some time studying relevant sections of the User Guides
from Motorola, but have had a difficult time putting all the pieces together.
Can anyone recommend a good book that covers these sorts of issues, for the
68030 and 68882 chips as well?
Thanks,
Tim Dorcey