Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!samsung!dali.cs.montana.edu!milton!whit From: whit@milton.u.washington.edu (John Whitmore) Newsgroups: sci.electronics Subject: Re: Oscillators with extra-large frequency ranges Message-ID: <13909@milton.u.washington.edu> Date: 7 Jan 91 22:49:23 GMT References: Distribution: sci.electronics Organization: University of Washington, Seattle Lines: 40 In article mlukka@lut.fi (Markku Lukka) writes: >For a certain project, I would need an oscillator with digital, >LOGARITHMIC adjusting (32-bit, 1000 x log) and a HUGE range, >1 kHz to 100 MHz. Is this at all possible? Barely possible, and probably not very stable. There's an RCA application note (search in old RCA applications literature) on building a wide-range oscillator (roughly 1 Hz to 1 MHz) from their CA3080 transconductance amplifier. The basic principle is phase-shift oscillation, with the output impedance of the amplifier and the capacitive load providing the phase shift. The programming current is the frequency control. This programming current goes into the base of a grounded-emitter transistor, so the Vbe on that transistor is a logarithmic voltage signal (and with an op amp, you can use that as the logarithm adjusting generator you refer to; exercise for the reader). In the 1977 RCA linear databook, the oscillator is described in Fig. 23, p. 169 (part of the CA3080 data sheet). As a practical matter, you'll need a thermostat on the logarithm transistor (because the transfer curve is temperature dependent as well as logarithmic), and your noise (a few nanovolts) might NOT be negligible on the voltage-control input. The stray capacitance of each amplifier stage will affect the frequency (drift is likely). Normally, wide-range VCOs use several narrow-band VCOs and switch from one to another (for TV, three bands suffices). >Then the next problem would be just to divide this signal into eight >lines, so that the lines would pulse (change state, whichever would be >the easiest) alternately, in order. I mean: Line 1,then line 2, then line 3, Well, that's possible if you use an eight-stage phase shift network (three is more typical). Alternately, you can consider a higher-frequency phase-locked signal with a 'twisted ring' counter. Eight D flip-flops with each Q connected to the next D, and the final /Q connected to the first D, all clocked by 8x the highest frequency you want, would do it. That means 800 MHz clock rates, just barely possible with fast logic. GaAs or ECL of course (TTL is hopeless at this frequency). John Whitmore