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From: ma@stl.stc.co.uk
Newsgroups: sci.electronics
Subject: Problem interpreting M68HC11 documentation
Message-ID: <3902@stl.stc.co.uk>
Date: 8 Jan 91 09:36:02 GMT
Sender: news@stl.stc.co.uk
Reply-To: ma@stl.stc.co.uk ()
Organization: STC Technology Limited, London Road, Harlow, Essex, UK
Lines: 63

I am using the Motorola M68HC11 in an amateur project, but am having
great difficulty in decoding the documentation (the reference manual,
and the technical summary for the version I am using, MC68HC11A0).  I
wonder if others on the net have experience with this processor, and
could enlighten me.

I am using an external CMOS RAM as program memory, and using the
processor's bootstrap mode to load the RAM from a PC via the serial
line.  I will probably replace the RAM with an EPROM once I have
finalised the software.

My problem is that it is unclear what state the data bus is in when
the processor is reset in bootstrap mode, and if I need to take any
precautions to prevent contention between the bootstrap ROM and
external RAM which occupy the same address.

The manual states two things, in different places.  (1) It states
that bootstrap mode is a special version of single chip mode, in which
ports B and C are used as programmable peripheral ports.  This would
mean that the multiplexed low address/data bus will start off in input
mode, and the high address bus will be set to zeros.  (2) It also
states that the default value of the IRV (internal read visibility)
bit in the HPRIO register is 1 in the bootstrap mode, and that when
IRV is set internal reads cause the external data bus to be driven
with the data read internally (for debugging purposes).  This could
lead to contention between the internal bootstrap ROM, and external
RAM at the same address.

Can anyone enlighten me which is correct, (1) or (2)?  The processor I
have seems to follow (1), but can I be sure that all future processors
will keep to interpretation (1)?

As a supplementary question, I assume that I need to put pull-up
resistors on the data bus, to prevent excessive currents in CMOS bus
receivers if the bus floats in an intermediate logic state.  However,
because my system is battery powered, I do not want excessive
dissipation in these resistors.  Is it reasonable to use very high
values (perhaps 1 Meg)?  Alternatively, is it reasonable to bootstrap
the load resistors (in the electronic, rather than software sense!)
with a circuit like:

                                 |\ 
                                 | \        10K
            To data bus  <---+---|  >------/\/\/\---+
                             |   | /                |
                             |   |/ Non-inverting   |
                             |         buffer       |
                             |                      |
                             +----------------------+

I've never seen such a circuit used (although I must admit that I
specialise in software, not hardware!) but it does seem to be a neat
way of minimising dissipation in the pullup/pulldown resistors while
keeping the bus in a legal state.

Perhaps you could reply by mail -- I will summarise any replies I get
to the net.

Regards

Melvin Anderson      <ma@stl.stc.co.uk>

STC Technology Ltd., London Road, Harlow, Essex, England.