Path: utzoo!utgpu!news-server.csri.toronto.edu!bonnie.concordia.ca!uunet!mcsun!ukc!edcastle!cs.ed.ac.uk!cs.edinburgh.ac.uk!ddr
From: ddr@cs.edinburgh.ac.uk (Doug Rogers)
Newsgroups: comp.arch
Subject: Re: Stack Cache with O/S driven copyback ?
Keywords: stack cache caching
Message-ID: <4513@skye.cs.ed.ac.uk>
Date: 15 Jan 91 11:09:15 GMT
References: <5229@bwdls58.UUCP>
Sender: nnews@cs.ed.ac.uk
Reply-To: ddr@cs.edinburgh.ac.uk (Doug Rogers)
Organization: Department of Computer Science, University of Edinburgh
Lines: 25

In article <5229@bwdls58.UUCP>, mlord@bwdls58.UUCP (Mark Lord) writes:
> How smart are the stack-cache designs that have been looked at?
> I'm curious whether a proposal such as the following has already
> been researched.
> 
> Specifically, how about an operating system controlled cache, devoted to
> caching the call stack of the current task and/or interrupt handler?
> 
> This stack would have the following key characteristics:
> 
> 	5) copyback has lowest bus priority - gets done only when nothing
> 		else wants the bus (reads, writes, dma, other caches).

The problem is in multi processor systems maintaining cache consistency. Within
the Futurebus spec. one user has the right to modify at any time. Clearly
if there was only one copy of the information then it should not matter how slowly
the information is passed back but what happens if while this is going on another
cache wishes to gain access to this information. (this would include the data cache
for the same processor).

-- 
Douglas Rogers                     JANET: ddr@uk.ac.ed.lfcs
Department of Computer Science     UUCP:  ..!mcvax!ukc!lfcs!ddr
University of Edinburgh            ARPA:  ddr%lfcs.ed.ac.uk@nsfnet-relay.ac.uk
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