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From: mhjohn@aspen.IAG.HP.COM (Mark Johnson)
Newsgroups: comp.arch
Subject: Re: Controller registers vs. Speculative Execution
Message-ID: <1360006@aspen.IAG.HP.COM>
Date: 18 Jan 91 22:51:28 GMT
References: <14829@celit.fps.com>
Organization: Information Architecture Group, HP
Lines: 23

In comp.arch, lindsay@gandalf.cs.cmu.edu (Donald Lindsay) writes:

    As to what the CPU does about it .. the main requirement is that
    uncached speculative reads not be done. (There's no such thing as a
    speculative write, because in general you don't know the prior
    contents of the memory location, and hence, there is no reasonable
    way to undo the write.)

There certainly can be such a thing as speculative writes.  Any design
that includes a write buffer can also speculatively execute a write.
The buffer would not dump the information to memory until the
speculative operation was committed.  If the speculative operation is
not needed, the write is never done.

Speculative execution would not have to stall on writes, which occur
with about a 1 in 7 frequency on the architecture I last looked at.

Write buffers are a common way of integrating a very fast execution
unit to a slower main memory.  The one's I am familiar with were
designed to be completely software transparent.  They are a handy
place to accommodate unaligned writes, gather sequential writes into
a wider write, merging direct I/O with programmed
writes, etc.