Path: utzoo!utgpu!news-server.csri.toronto.edu!bonnie.concordia.ca!uunet!mcsun!ukc!cam-cl!news
From: cet1@cl.cam.ac.uk (C.E. Thompson)
Newsgroups: comp.arch
Subject: Re: Controller registers vs. Speculative Execution
Message-ID: <1991Jan21.142422.17655@cl.cam.ac.uk>
Date: 21 Jan 91 14:24:22 GMT
References: <14829@celit.fps.com> <1360006@aspen.IAG.HP.COM> <11625@pt.cs.cmu.edu>
Reply-To: cet1@cl.cam.ac.uk (C.E. Thompson)
Organization: U of Cambridge Comp Lab, UK
Lines: 34

In article <11625@pt.cs.cmu.edu> lindsay@gandalf.cs.cmu.edu (Donald Lindsay) writes:
>Yes, I was simplifying. For example, see "RISC System/6000 Hardware
>Overview":
>
>"...a five entry pending store queue and a four-entry store data
>queue in the FPU enable the FXU [integer unit] to execute floating-
>point store operations before the FPU produces the data. This allows
>the FXU to generate the address, initiate TLB or cache reload
>sequences, and check for data protection for a floating-point store
>instruction, and then continue executing the subsequent instructions
>without being held back by the FPU."
>
>Note that this machine isn't even advertised as a speculative-
>execution design - merely a parallel one. One wonders about the
>sequencing of FPU and MMU interrupts, and about how much more fun the
>design could be if some of those stores were conditional. And then
>there's the classical problem of matching the addresses of reads
>against the addresses with pending writes.

But this isn't speculative execution of writes at all! It is simply early
detection of exceptions: the FXU address calculation cycle happens first
and all possible (storage access) exceptions happen then. Thereafter
the store operation sits around in the PSQ until the FPU gets around
to delivering the data, but the store is absolutely guaranteed to complete.
(There are some details I haven't seen any documentation on, admittedly,
such as how the FXU makes sure that the required line is still in the  
cache later on, and hasn't been flushed by intermediate FXU storage accesses.)
In fact, the RS/6000 isn't advertised as a speculative-execution design
because it isn't one. Unless you count "conditional dispatching" as 
speculative excecution, which I certainly wouldn't.

Chris Thompson
JANET:    cet1@uk.ac.cam.phx
Internet: cet1%phx.cam.ac.uk@nsfnet-relay.ac.uk