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From: lindsay@gandalf.cs.cmu.edu (Donald Lindsay)
Newsgroups: comp.arch
Subject: Re: Controller registers vs. Speculative Execution
Message-ID: <11651@pt.cs.cmu.edu>
Date: 23 Jan 91 02:33:05 GMT
References: <11625@pt.cs.cmu.edu> <1991Jan21.142422.17655@cl.cam.ac.uk>
Organization: Carnegie Mellon Robotics Institute
Lines: 42


In article <1991Jan21.142422.17655@cl.cam.ac.uk>
	cet1@cl.cam.ac.uk (C.E. Thompson) writes:
>>"...a five entry pending store queue and a four-entry store data
>>queue in the FPU enable the FXU [integer unit] to execute floating-
>>point store operations before the FPU produces the data. This allows
>>the FXU to generate the address, initiate TLB or cache reload
>>sequences, and check for data protection for a floating-point store
>>instruction, and then continue executing the subsequent instructions
>>without being held back by the FPU."
>>
>>Note that this machine isn't even advertised as a speculative-
>>execution design - merely a parallel one. One wonders about the
>>sequencing of FPU and MMU interrupts, and about how much more fun the
>>design could be if some of those stores were conditional. And then
>>there's the classical problem of matching the addresses of reads
>>against the addresses with pending writes.
>
>But this isn't speculative execution of writes at all! 

Yes, that's what I said. The design issues raised by this machine
would be that much more difficult if some of the stores were
initiated speculatively, and could not be committed until a third
execution unit (the branch unit) signalled permission. For one thing,
one normally tries to do writes in order (hence, the RIOS uses
queues). But, if some writes were stalled on conditions, I can quite
imagine IBM adding queue-jumping logic.

>It is simply early detection of exceptions:

There's still the ordering issue. The FXU and FPU execute from queues
of issued instructions, and either may be ahead. If a particular
instruction is capable of causing two exceptions, which one is
raised?

>(There are some details I haven't seen any documentation on, admittedly,
>such as how the FXU makes sure that the required line is still in the  
>cache later on, and hasn't been flushed by intermediate FXU storage accesses.)

Interesting issue.
-- 
Don		D.C.Lindsay .. temporarily at Carnegie Mellon Robotics